EP1810JI-35 vs EP1810JI-45 तुलना
विस्तृत दोनों ओर की तुलना EP1810JI-35 द्वारा Intel और EP1810JI-45 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP1810JI-35 | EP1810JI-45 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | — |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| पैकेज | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| ऑपरेटिंग तापमान | -40C to +85C (Industrial) | -40 °C to +85 °C |
| सप्लाई वोल्टेज | 5 V (typical classic EPLD) | 5 V (TTL compatible) |
| Programmability | UV-erase, windowed for lab reprogram | — |
| माउंटिंग प्रकार | Through-Hole (J-lead) | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | — |
| MSL स्तर | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 50 ns |
| Configurable I/O Lines | — | 48 |
| Technology | — | CMOS EPROM |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |