EP1810JI-35 vs EP1810JI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810JI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-35 | EP1810JI-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | — |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Packhaging | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40 °C to +85 °C |
| Volte ng Pagbibigay | 5 V (typical classic EPLD) | 5 V (TTL compatible) |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Uri ng Pagpapasok | Through-Hole (J-lead) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 50 ns |
| Configurable I/O Lines | — | 48 |
| Technology | — | CMOS EPROM |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |