EP1SGX25FF1020I7N vs EP1SGX25FF1020I7 तुलना
विस्तृत दोनों ओर की तुलना EP1SGX25FF1020I7N द्वारा Intel और EP1SGX25FF1020I7 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EP1SGX25FF1020I7 - Stratix GX FPGA 25,660 Cells, 1.5V, FC-FBGA-1020 | Altera / Intel
EP1SGX25FF1020I7 Obsoleteविशेषता तुलना
| पैरामीटर | EP1SGX25FF1020I7N | EP1SGX25FF1020I7 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Product Family | Stratix GX | — |
| Logic Family | CMOS | — |
| Number of Logic Cells | 25,660 | — |
| Number of CLBs | 2,566 | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Number of Terminals | 1020 | — |
| Terminal Form | Ball | Ball |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Package Body | 33 x 33 mm, 1.0 mm pitch, FBGA-1020, lead-free | — |
| ऑपरेटिंग तापमान रेंज | 0 to 85 °C (DigChip excerpt for this MPN) | — |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount (FC-FBGA) |
| Embedded Memory Bits | [DATA_NEEDED: embedded memory bits] | — |
| अधिकतम क्लॉक फ़्रीक्वेंसी | [DATA_NEEDED: maximum clock frequency] | — |
| Number of Multi-Gigabit Transceivers | [DATA_NEEDED: transceiver count] | — |
| User I/O Count | [DATA_NEEDED: user I/O count] | — |
| RoHS / Lead-Free | Lead-free finish indicated by N suffix; complete RoHS status [DATA_NEEDED: full RoHS certificate status] | — |
| MSL स्तर | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| लाइफसाइकिल स्थिति | Obsolete / NRND (Stratix GX family end-of-life) | — |
| Family | — | Stratix GX |
| Series | — | EP1SGX25 |
| Logic Cells | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,566 |
| पैकेज | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Number of Terminals / Balls | — | 1020 |
| Temperature Grade (suffix 'I') | — | Industrial |
| Speed Grade | — | 7 (highest production grade) |
| Terminal Pitch | — | [DATA_NEEDED: terminal pitch] |
| Combinatorial Delay per CLB | — | 9.48 ns (per Microchip USA listing) |
| Combinatorial Delay Variant | — | [DATA_NEEDED: tPD per CLB variant speed grade] |
| Maximum Internal Clock Frequency | — | [DATA_NEEDED: max Fmax in MHz per speed grade] |
| Embedded Transceivers | — | Yes (Stratix GX feature) |
| Configuration Method | — | SRAM-based (volatile, requires configuration at power-up) |
| RoHS स्थिति | — | [DATA_NEEDED: RoHS compliance] |