EP1SGX25FF1020I7N vs EP1SGX25FF1020I7 비교
다음의 상세 나란히 비교: EP1SGX25FF1020I7N 제조: Intel 및 EP1SGX25FF1020I7 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EP1SGX25FF1020I7 - Stratix GX FPGA 25,660 Cells, 1.5V, FC-FBGA-1020 | Altera / Intel
EP1SGX25FF1020I7 Obsolete사양 비교
| 파라미터 | EP1SGX25FF1020I7N | EP1SGX25FF1020I7 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $98.50 | $210.00 |
| Product Family | Stratix GX | — |
| Logic Family | CMOS | — |
| Number of Logic Cells | 25,660 | — |
| Number of CLBs | 2,566 | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Number of Terminals | 1020 | — |
| Terminal Form | Ball | Ball |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Package Body | 33 x 33 mm, 1.0 mm pitch, FBGA-1020, lead-free | — |
| 동작 온도 범위 | 0 to 85 °C (DigChip excerpt for this MPN) | — |
| 실장 유형 | Surface Mount (BGA) | Surface Mount (FC-FBGA) |
| Embedded Memory Bits | [DATA_NEEDED: embedded memory bits] | — |
| 최대 클록 주파수 | [DATA_NEEDED: maximum clock frequency] | — |
| Number of Multi-Gigabit Transceivers | [DATA_NEEDED: transceiver count] | — |
| User I/O Count | [DATA_NEEDED: user I/O count] | — |
| RoHS / Lead-Free | Lead-free finish indicated by N suffix; complete RoHS status [DATA_NEEDED: full RoHS certificate status] | — |
| MSL 레벨 | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| 수명 주기 상태 | Obsolete / NRND (Stratix GX family end-of-life) | — |
| Family | — | Stratix GX |
| Series | — | EP1SGX25 |
| Logic Cells | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,566 |
| 패키지 | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Number of Terminals / Balls | — | 1020 |
| Temperature Grade (suffix 'I') | — | Industrial |
| Speed Grade | — | 7 (highest production grade) |
| Terminal Pitch | — | [DATA_NEEDED: terminal pitch] |
| Combinatorial Delay per CLB | — | 9.48 ns (per Microchip USA listing) |
| Combinatorial Delay Variant | — | [DATA_NEEDED: tPD per CLB variant speed grade] |
| Maximum Internal Clock Frequency | — | [DATA_NEEDED: max Fmax in MHz per speed grade] |
| Embedded Transceivers | — | Yes (Stratix GX feature) |
| Configuration Method | — | SRAM-based (volatile, requires configuration at power-up) |
| RoHS 상태 | — | [DATA_NEEDED: RoHS compliance] |