EP910DI-35 vs EP910IDC-15 तुलना
विस्तृत दोनों ओर की तुलना EP910DI-35 द्वारा Altera और EP910IDC-15 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910DI-35 | EP910IDC-15 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 10 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| पैकेज | CDIP-40 (Ceramic DIP with UV window) | 40-pin CDIP (Ceramic DIP, through-hole) |
| माउंटिंग प्रकार | Through-Hole | — |
| ऑपरेटिंग तापमान | -40C to +85C (industrial) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | — |
| Erasure Method | UV light through quartz window | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | non_compliant (ceramic DIP contains lead) |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| I/O Pins | — | 24 |
| Programming Technology | — | EPROM (UV-erasable) |