EP910DI-35 vs EP910IDC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DI-35 disebabkan oleh Altera dan EP910IDC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910DI-35 EP910IDC-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 10
Bidirectional I/O Pins 20 —
Total Pins 40 —
Kemasan CDIP-40 (Ceramic DIP with UV window) 40-pin CDIP (Ceramic DIP, through-hole)
Jenis Pemasangan Through-Hole —
Suhu Operasi -40C to +85C (industrial) —
Technology CMOS, UV-erasable EPROM —
Programming Method EPROM programmer + JEDEC fuse map —
Erasure Method UV light through quartz window —
Status RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] non_compliant (ceramic DIP contains lead)
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC Altera (now Intel PSG)
Equivalent Gates — 450
Flip-Flops — 48
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fCNT) — 66.6 MHz
Terminal Count — 40
Terminal Form — Through-Hole
Temperature Grade — Commercial (0C to +70C)
Programmable Security Bit — Yes
On-board Test Circuitry — Yes
Logic Type — UV Erasable EPROM-based
I/O Pins — 24
Programming Technology — EPROM (UV-erasable)

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