EP910DI-35 vs EP910IDC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-35 sa pamamagitan ng Altera at EP910IDC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DI-35 EP910IDC-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 10
Bidirectional I/O Pins 20 —
Total Pins 40 —
Packhaging CDIP-40 (Ceramic DIP with UV window) 40-pin CDIP (Ceramic DIP, through-hole)
Uri ng Pagpapasok Through-Hole —
Temperature na Operasyon -40C to +85C (industrial) —
Technology CMOS, UV-erasable EPROM —
Programming Method EPROM programmer + JEDEC fuse map —
Erasure Method UV light through quartz window —
Tindminan RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] non_compliant (ceramic DIP contains lead)
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC Altera (now Intel PSG)
Equivalent Gates — 450
Flip-Flops — 48
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fCNT) — 66.6 MHz
Terminal Count — 40
Terminal Form — Through-Hole
Temperature Grade — Commercial (0C to +70C)
Programmable Security Bit — Yes
On-board Test Circuitry — Yes
Logic Type — UV Erasable EPROM-based
I/O Pins — 24
Programming Technology — EPROM (UV-erasable)

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