EP910IPC-15 vs EP910IPC-50 तुलना
विस्तृत दोनों ओर की तुलना EP910IPC-15 द्वारा Altera और EP910IPC-50 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910IPC-15 | EP910IPC-50 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 50 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| ऑपरेटिंग तापमान | 0C to +70C (commercial, IPC suffix) | -40C to +85C (industrial) |
| पैकेज | PDIP-40 (Plastic DIP, 40-pin) | 40-pin Ceramic DIP (IPC, windowed) |
| माउंटिंग प्रकार | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | Off-board EPROM programmer + UV erase |
| पिन काउंट | 40 | — |
| RoHS स्थिति | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: not stated in verified data] |
| Family | — | Altera Classic EPLD |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Technology | — | CMOS EPROM cell |
| Erasure Method | — | UV light through ceramic window (IPC package) |