EP910IPC-15 vs EP910IPC-50 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-15 sa pamamagitan ng Altera at EP910IPC-50 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-15 | EP910IPC-50 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 50 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Temperature na Operasyon | 0C to +70C (commercial, IPC suffix) | -40C to +85C (industrial) |
| Packhaging | PDIP-40 (Plastic DIP, 40-pin) | 40-pin Ceramic DIP (IPC, windowed) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | Off-board EPROM programmer + UV erase |
| Bilang ng Pin | 40 | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: not stated in verified data] |
| Family | — | Altera Classic EPLD |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Technology | — | CMOS EPROM cell |
| Erasure Method | — | UV light through ceramic window (IPC package) |