EP910LC44-40 vs EP910LC44 तुलना
विस्तृत दोनों ओर की तुलना EP910LC44-40 द्वारा Altera और EP910LC44 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910LC44-40 | EP910LC44 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | अंतिम बार खरीदें |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Product Terms (Total) | 240 | — |
| I/O Pins | 24 (bidirectional) | 24 |
| Dedicated Inputs | 12 | 12 |
| Total Inputs | 36 | — |
| Global Clock Inputs | 2 | 2 |
| Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Compatibility | TTL-compatible I/O | TTL-compatible CMOS I/O |
| पैकेज | 44-pin PLCC (Plastic Leaded Chip Carrier) | 44-pin PLCC (J-leaded) |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Programming Method | JEDEC file via LP6/MP9 or compatible programmer | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| माउंटिंग प्रकार | Surface Mount | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified data] |
| Product Family | — | Classic EPLD (EP910 Series) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |