EP910LC44-40 vs EP910LC44 比較
詳細並排比較 EP910LC44-40 由 Altera 與 EP910LC44 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC44-40 | EP910LC44 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Product Terms (Total) | 240 | — |
| I/O Pins | 24 (bidirectional) | 24 |
| Dedicated Inputs | 12 | 12 |
| Total Inputs | 36 | — |
| Global Clock Inputs | 2 | 2 |
| Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable EPROM | — |
| Logic Compatibility | TTL-compatible I/O | TTL-compatible CMOS I/O |
| 封裝 | 44-pin PLCC (Plastic Leaded Chip Carrier) | 44-pin PLCC (J-leaded) |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] |
| Programming Method | JEDEC file via LP6/MP9 or compatible programmer | EPROM (erasable UV for ceramic; OTP for plastic PLCC) |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified data] |
| Product Family | — | Classic EPLD (EP910 Series) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Total Product Terms | — | 240 |
| Total Input Pins | — | 36 (12 dedicated + 24 I/O as inputs) |
| Propagation Delay (LC grade) | — | [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] |
| Propagation Delay (LC-30 grade) | — | 33 ns (per EP910LC44-30 verified data) |
| Process Technology | — | CMOS |
| Architecture | — | AND-OR sum-of-products with programmable macrocell feedback |