EP910LI-20 vs EP910IPC-50 तुलना
विस्तृत दोनों ओर की तुलना EP910LI-20 द्वारा Altera और EP910IPC-50 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910LI-20 | EP910IPC-50 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Maximum Operating Frequency | 62 MHz | — |
| Propagation Delay (tpd) | 20 ns | — |
| Dedicated Inputs | 16 | — |
| I/O Pins | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| ऑपरेटिंग तापमान | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| पैकेज | 40-pin Ceramic DIP (Windowed) | 40-pin Ceramic DIP (IPC, windowed) |
| Technology | CMOS, UV-erasable | CMOS EPROM cell |
| Package Type | Through-Hole, Ceramic DIP with Quartz Window | — |
| Temperature Grade | Industrial (-40C to +85C) | — |
| पिन काउंट | 40 | — |
| Logic Family | EPLD (Erasable PLD) | — |
| Architecture | Sum-of-products macrocell | — |
| Pin/Package Compatibility | Pin-compatible across EP910 family | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Propagation Delay (tPD) | — | 50 ns |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |
| माउंटिंग प्रकार | — | Through-Hole (DIP) |