EP910LI-20 vs EP910IPC-50 比較
詳細並排比較 EP910LI-20 由 Altera 與 EP910IPC-50 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-20 | EP910IPC-50 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Maximum Operating Frequency | 62 MHz | — |
| Propagation Delay (tpd) | 20 ns | — |
| Dedicated Inputs | 16 | — |
| I/O Pins | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| 工作溫度 | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| 封裝 | 40-pin Ceramic DIP (Windowed) | 40-pin Ceramic DIP (IPC, windowed) |
| Technology | CMOS, UV-erasable | CMOS EPROM cell |
| Package Type | Through-Hole, Ceramic DIP with Quartz Window | — |
| Temperature Grade | Industrial (-40C to +85C) | — |
| 腳位數 | 40 | — |
| Logic Family | EPLD (Erasable PLD) | — |
| Architecture | Sum-of-products macrocell | — |
| Pin/Package Compatibility | Pin-compatible across EP910 family | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Propagation Delay (tPD) | — | 50 ns |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| User I/O Pins | — | 24 |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |
| 安裝類型 | — | Through-Hole (DIP) |