EP910LI-50 vs EP910LI44 तुलना
विस्तृत दोनों ओर की तुलना EP910LI-50 द्वारा Altera और EP910LI44 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910LI-50 | EP910LI44 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 50 ns | — |
| Package Type | CERDIP-40 (L) | PLCC-44 (J-lead, surface mount) |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) |
| ऑपरेटिंग तापमान | -40C to +85C (industrial) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Programming Method | EPROM programmer (UV-erasable window) | Altera Logic Programmer card / Data I/O / third-party EPROM programmers |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | non-compliant (original PLCC-44 lead finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Architecture | — | PAL-type, CMOS, One-Time-Programmable |
| Total Pins | — | 44 |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O | — | 24 |
| Maximum Logic Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Flip-Flops | — | 24 |
| External Clocks | — | 2 |
| Maximum Propagation Delay | — | [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] |
| Operating Temperature (L grade) | — | -40 °C to +85 °C (industrial) |
| Programmability | — | UV-erasable (windowed) or OTP |
| माउंटिंग प्रकार | — | Surface Mount (PLCC socket compatible) |