EP910PC-15T vs EP910PC-20T तुलना
विस्तृत दोनों ओर की तुलना EP910PC-15T द्वारा Altera और EP910PC-20T द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910PC-15T | EP910PC-20T |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Unknown |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | 20 ns |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| पैकेज | 40-pin PDIP (Plastic DIP) | — |
| माउंटिंग प्रकार | Through-hole (DIP) | — |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Device Type | — | EPLD |
| Fabrication Technology | — | CMOS |
| Logic Integration | — | 300 to 900 usable gates |
| Logic Emulation | — | 100% TTL emulation |
| Application Function | — | High-speed, low-power logic integration |
| Programmable Device Class | — | Erasable programmable logic device |
| Device Family | — | Altera Classic EPLD Family |
| Package Code | — | PC |
| Package Pin Count | — | [DATA_NEEDED: package pin count] |
| Package Dimensions | — | [DATA_NEEDED: package dimensions] |
| सप्लाई वोल्टेज | — | [DATA_NEEDED: operating supply voltage] |
| I/O Count | — | [DATA_NEEDED: I/O count] |
| Internal Logic Capacity | — | 300 to 900 usable gates |
| Supported Logic Integration | — | Multiple PAL- and GAL-type devices |
| Programming Interface | — | [DATA_NEEDED: programming interface] |
| Programming Voltage | — | [DATA_NEEDED: programming voltage] |
| Mounting Technology | — | [DATA_NEEDED: mounting technology] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |