EP910PC-15T vs EP910PC-20T موازنہ
تفصیلی ساتھ ساتھ موازنہ از EP910PC-15T بذریعہ Altera اور EP910PC-20T بذریعہ Altera. اہم خصوصیات، برقی پیرامیٹرز، پیکیجنگ، لائف سائیکل اسٹیٹس، قیمتوں اور دستیابی کا موازنہ کریں تاکہ آپ کی ڈیزائن ضروریات کے لیے بہترین کمپوننٹ کا تعین ہو سکے۔
خصوصیات کا موازنہ
| پیرامیٹر | EP910PC-15T | EP910PC-20T |
|---|---|---|
| برانڈ | Altera | Altera |
| زمرہ | FPGA & CPLD | FPGA & CPLD |
| لائف سائیکل کی حالت | Obsolete | Unknown |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocell Count | 24 | — |
| Dedicated Input Pins | 10 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Speed Grade | -15 (15 ns) | 20 ns |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| پیکیج | 40-pin PDIP (Plastic DIP) | — |
| ماؤنٹنگ ٹائپ | Through-hole (DIP) | — |
| Output Drive Current | [DATA_NEEDED: IOL per output] | — |
| آپریٹنگ درجہ حرارت | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Logic Capacity | 24 macrocells / 72 product terms (typical Classic architecture) | — |
| Programming Method | JEDEC fuse map via Altera LogicMap / MAX+PLUS II | — |
| RoHS اسٹیٹس | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Security Bit | Yes (design protection) | — |
| Tape and Reel | Yes (suffix T) | — |
| Device Type | — | EPLD |
| Fabrication Technology | — | CMOS |
| Logic Integration | — | 300 to 900 usable gates |
| Logic Emulation | — | 100% TTL emulation |
| Application Function | — | High-speed, low-power logic integration |
| Programmable Device Class | — | Erasable programmable logic device |
| Device Family | — | Altera Classic EPLD Family |
| Package Code | — | PC |
| Package Pin Count | — | [DATA_NEEDED: package pin count] |
| Package Dimensions | — | [DATA_NEEDED: package dimensions] |
| سپلائی وولٹیج | — | [DATA_NEEDED: operating supply voltage] |
| I/O Count | — | [DATA_NEEDED: I/O count] |
| Internal Logic Capacity | — | 300 to 900 usable gates |
| Supported Logic Integration | — | Multiple PAL- and GAL-type devices |
| Programming Interface | — | [DATA_NEEDED: programming interface] |
| Programming Voltage | — | [DATA_NEEDED: programming voltage] |
| Mounting Technology | — | [DATA_NEEDED: mounting technology] |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |