EP910PC-15T vs EP910PC-20T 比較

詳細並排比較 EP910PC-15T 由 Altera 與 EP910PC-20T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910PC-15T EP910PC-20T
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Unknown
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD
Macrocell Count 24 —
Dedicated Input Pins 10 —
Pin-to-Pin Delay (tPD) 15 ns —
Speed Grade -15 (15 ns) 20 ns
Supply Voltage (VCC) 5 V (nominal) —
Technology CMOS, UV-erasable / OTP —
封裝 40-pin PDIP (Plastic DIP) —
安裝類型 Through-hole (DIP) —
Output Drive Current [DATA_NEEDED: IOL per output] —
工作溫度 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Logic Capacity 24 macrocells / 72 product terms (typical Classic architecture) —
Programming Method JEDEC fuse map via Altera LogicMap / MAX+PLUS II —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Security Bit Yes (design protection) —
Tape and Reel Yes (suffix T) —
Device Type — EPLD
Fabrication Technology — CMOS
Logic Integration — 300 to 900 usable gates
Logic Emulation — 100% TTL emulation
Application Function — High-speed, low-power logic integration
Programmable Device Class — Erasable programmable logic device
Device Family — Altera Classic EPLD Family
Package Code — PC
Package Pin Count — [DATA_NEEDED: package pin count]
Package Dimensions — [DATA_NEEDED: package dimensions]
供應電壓 — [DATA_NEEDED: operating supply voltage]
I/O Count — [DATA_NEEDED: I/O count]
Internal Logic Capacity — 300 to 900 usable gates
Supported Logic Integration — Multiple PAL- and GAL-type devices
Programming Interface — [DATA_NEEDED: programming interface]
Programming Voltage — [DATA_NEEDED: programming voltage]
Mounting Technology — [DATA_NEEDED: mounting technology]
REACH Status — unknown
AEC-Q100 Qualification — not_applicable
Lead-Free Status — unknown
Halogen-Free Status — unknown

資料表與資源

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