EP910PC-20T vs EP910PC-20 तुलना
विस्तृत दोनों ओर की तुलना EP910PC-20T द्वारा Altera और EP910PC-20 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910PC-20T | EP910PC-20 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Unknown | Obsolete |
| Device Type | EPLD | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Fabrication Technology | CMOS | — |
| Logic Integration | 300 to 900 usable gates | — |
| Logic Emulation | 100% TTL emulation | — |
| Application Function | High-speed, low-power logic integration | — |
| Programmable Device Class | Erasable programmable logic device | — |
| Device Family | Altera Classic EPLD Family | — |
| Speed Grade | 20 ns | — |
| Package Code | PC | — |
| Package Pin Count | [DATA_NEEDED: package pin count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| सप्लाई वोल्टेज | [DATA_NEEDED: operating supply voltage] | — |
| ऑपरेटिंग तापमान | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Internal Logic Capacity | 300 to 900 usable gates | — |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | — |
| Programming Interface | [DATA_NEEDED: programming interface] | — |
| Programming Voltage | [DATA_NEEDED: programming voltage] | — |
| Mounting Technology | [DATA_NEEDED: mounting technology] | — |
| RoHS स्थिति | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| पैकेज | — | PDIP-24 (PC suffix) |
| पिन काउंट | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Programming Method | — | EPROM programmer, JEDEC fuse map |
| माउंटिंग प्रकार | — | Through-Hole (DIP) |
| MSL स्तर | — | [DATA_NEEDED: MSL level] |