EP910PC-20T vs EP910PC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-20T sa pamamagitan ng Altera at EP910PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-20T | EP910PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Unknown | Obsolete |
| Device Type | EPLD | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Fabrication Technology | CMOS | — |
| Logic Integration | 300 to 900 usable gates | — |
| Logic Emulation | 100% TTL emulation | — |
| Application Function | High-speed, low-power logic integration | — |
| Programmable Device Class | Erasable programmable logic device | — |
| Device Family | Altera Classic EPLD Family | — |
| Speed Grade | 20 ns | — |
| Package Code | PC | — |
| Package Pin Count | [DATA_NEEDED: package pin count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Volte ng Pagbibigay | [DATA_NEEDED: operating supply voltage] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Internal Logic Capacity | 300 to 900 usable gates | — |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | — |
| Programming Interface | [DATA_NEEDED: programming interface] | — |
| Programming Voltage | [DATA_NEEDED: programming voltage] | — |
| Mounting Technology | [DATA_NEEDED: mounting technology] | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Device | — | EP910 |
| Usable Gates | — | 900 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Packhaging | — | PDIP-24 (PC suffix) |
| Bilang ng Pin | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EPROM (UV-erasable) |
| I/O Compatibility | — | 100% TTL |
| Programming Method | — | EPROM programmer, JEDEC fuse map |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |