EPC20LC20U vs EPC16UC88 तुलना
विस्तृत दोनों ओर की तुलना EPC20LC20U द्वारा Intel और EPC16UC88 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPC20LC20U | EPC16UC88 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | Memory ICs | Memory ICs |
| लाइफसाइकिल स्थिति | Obsolete | Unknown |
| Manufacturer | Altera Corporation (now Intel) | — |
| फ़ंक्शन | FPGA Configuration Device (Serial Configuration PROM) | — |
| मेमोरी प्रकार | Non-volatile configuration memory | — |
| Configuration Interface | Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) | — |
| Operating Voltage | 5.0 V (typical) | — |
| Absolute Maximum DC Input | -0.3 V to 7.0 V | — |
| Transient Input Tolerance | -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) | — |
| Package Type | PLCC-20 (J-lead, plastic leaded chip carrier) | — |
| पिन काउंट | 20 | — |
| माउंटिंग प्रकार | Surface Mount (PLCC socket compatible) | Surface mount |
| Compatible FPGA Families | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone | — |
| In-System Programming | Supported via JTAG / Quartus programmer | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| ऑपरेटिंग तापमान रेंज | [DATA_NEEDED: industrial/commercial grade] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| लाइफसाइकिल स्थिति | Obsolete / Last-time-buy in distribution | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| सप्लाई वोल्टेज | — | 3.3 V core and I/O |
| पैकेज | — | 88-UBGA (11x8) |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| ऑपरेटिंग तापमान | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |