EPC20LC20U vs EPC16UC88 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC20LC20U sa pamamagitan ng Intel at EPC16UC88 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC20LC20U | EPC16UC88 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Unknown |
| Manufacturer | Altera Corporation (now Intel) | — |
| Fungsi | FPGA Configuration Device (Serial Configuration PROM) | — |
| Uri ng Memory | Non-volatile configuration memory | — |
| Configuration Interface | Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) | — |
| Operating Voltage | 5.0 V (typical) | — |
| Absolute Maximum DC Input | -0.3 V to 7.0 V | — |
| Transient Input Tolerance | -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) | — |
| Package Type | PLCC-20 (J-lead, plastic leaded chip carrier) | — |
| Bilang ng Pin | 20 | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface mount |
| Compatible FPGA Families | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone | — |
| In-System Programming | Supported via JTAG / Quartus programmer | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: industrial/commercial grade] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Katayuan ng Lifecycle | Obsolete / Last-time-buy in distribution | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Volte ng Pagbibigay | — | 3.3 V core and I/O |
| Packhaging | — | 88-UBGA (11x8) |
| Package Family | — | UBGA |
| In-System Programmability | — | IEEE Std. 1532 compatible |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |