EPM5064JC1 vs EPM5064LC-2 तुलना
विस्तृत दोनों ओर की तुलना EPM5064JC1 द्वारा Altera और EPM5064LC-2 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5064JC1 | EPM5064LC-2 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD / EPLD (Erasable PLD) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1.25K | — |
| Maximum Operating Frequency (fCNT) | 62.5 MHz | — |
| External Clock Input (max) | 50 MHz | — |
| I/O Pins | 28 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 36 (28 I/O + 7 dedicated + 1 clock) | — |
| Operating Voltage (VCC) | 5 V | — |
| Program Type | EPROM (one-time programmable, UV-erasable) | — |
| Process Technology | CMOS | CMOS, OTP EPROM (UV-erasable base) |
| पैकेज | 44-pin PLCC (J-Lead) | PLCC-44 (J-Lead, plastic) |
| Operating Temperature (JC suffix) | 0°C to +70°C (commercial) | — |
| Supply Current (ICC) | [DATA_NEEDED: ICC maximum] | — |
| RoHS स्थिति | unknown | [DATA_NEEDED: not specified in source] |
| Lead-Free Status | unknown | — |
| Device Family | — | MAX 5000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements per LAB | — | 16 |
| Number of Inputs | — | 36 (7 dedicated + 28 I/O) |
| Number of I/O Pins | — | 28 |
| Number of Flip-Flops | — | 28 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Internal Frequency | — | 40 MHz |
| Programmable Polarity | — | Yes |
| Programmable Output Enable | — | Yes, per macrocell |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| ऑपरेटिंग तापमान | — | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] |
| माउंटिंग प्रकार | — | Surface Mount |
| Programming Method | — | Altera byte-wide / JTAG programmer |