EPM9320LC84-10 vs EPM9320ALC84-10 तुलना
विस्तृत दोनों ओर की तुलना EPM9320LC84-10 द्वारा Intel और EPM9320ALC84-10 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM9320LC84-10 | EPM9320ALC84-10 |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | Obsolete |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | EPM9320 |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 168 (varies by package) | 52 |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | — |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM | — |
| पैकेज | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC (J-Lead) |
| माउंटिंग प्रकार | Surface Mount (PLCC socket also common) | Surface Mount / Through-Hole (PLCC socket) |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | [DATA_NEEDED: commercial/industrial grade] |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | — |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| RoHS स्थिति | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED] |
| नमी संवेदनशीलता स्तर (MSL) | MSL-3, 168 hours (per fpgalink listing) | — |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | — |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |
| Architecture | — | MAX (Multiple Array MatriX) with FastTrack Interconnect |