EPM9320LC84-10 vs EPM9320ALC84-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-10 sa pamamagitan ng Intel at EPM9320ALC84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320LC84-10 | EPM9320ALC84-10 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | EPM9320 |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 168 (varies by package) | 52 |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | — |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM | — |
| Packhaging | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket also common) | Surface Mount / Through-Hole (PLCC socket) |
| Temperature na Operasyon | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | [DATA_NEEDED: commercial/industrial grade] |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | — |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| Tindminan RoHS | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | MSL-3, 168 hours (per fpgalink listing) | — |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | — |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |
| Architecture | — | MAX (Multiple Array MatriX) with FastTrack Interconnect |