EPM9560RC240-20 vs EPM9560RC240-1O तुलना
विस्तृत दोनों ओर की तुलना EPM9560RC240-20 द्वारा Intel और EPM9560RC240-1O द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EPM9560RC240-20 - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
EPM9560RC240-20 ObsoleteIntel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O ⚠ अंतिम खरीदविशेषता तुलना
| पैरामीटर | EPM9560RC240-20 | EPM9560RC240-1O |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | अंतिम बार खरीदें |
| Family | MAX 9000 | MAX 9000 |
| Series | MAX 9000 PLD Family | — |
| Programmable Type | In System Programmable | — |
| Number of Macrocells | 560 | — |
| Number of Gates | 12,000 | — |
| Number of Logic Elements/Blocks | 35 LABs | — |
| Number of User I/Os | 191 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Maximum Internal Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Technology | CMOS, EEPROM-based | — |
| ऑपरेटिंग तापमान | 0C to 70C (Commercial) | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| पैकेज / केस | 240-BFQFP Exposed Pad (RQFP-240) | — |
| Supplier Device Package | 240-RQFP | — |
| Programming Interface | JTAG (IEEE 1149.1), Altera proprietary | — |
| Product Status | Obsolete | — |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status for this lot] | — |
| Usable Gates | — | 12,000 |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 216 |
| Propagation Delay (tPD) | — | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | — | 3.0 ns |
| Clock-to-Output (tFCO) | — | 4.8 ns |
| Maximum Internal Frequency (fCNT) | — | 145 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Grade) | — | -40C to +85C (industrial, "-1O" suffix) |
| Process Technology | — | CMOS EEPROM, 0.65 um |
| Programming | — | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array MatriX (MAX), third generation |
| पैकेज | — | RQFP-240 (240-pin Reduced-height QFP) |
| RoHS स्थिति | — | Compliant (per Altera/Intel product page) |
| Lead-Free | — | Yes |