EPM9560RC240-20 vs EPM9560RC240-1O Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-20 sa pamamagitan ng Intel at EPM9560RC240-1O sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC240-20 EPM9560RC240-1O
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 9000 MAX 9000
Series MAX 9000 PLD Family —
Programmable Type In System Programmable —
Number of Macrocells 560 —
Number of Gates 12,000 —
Number of Logic Elements/Blocks 35 LABs —
Number of User I/Os 191 —
Propagation Delay (tPD max) 20 ns —
Maximum Internal Frequency 100 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
Technology CMOS, EEPROM-based —
Temperature na Operasyon 0C to 70C (Commercial) —
Uri ng Pagpapasok Surface Mount Surface Mount
Packhaging / Kaso 240-BFQFP Exposed Pad (RQFP-240) —
Supplier Device Package 240-RQFP —
Programming Interface JTAG (IEEE 1149.1), Altera proprietary —
Product Status Obsolete —
Lead-Free / RoHS [DATA_NEEDED: RoHS status for this lot] —
Usable Gates — 12,000
Macrocells — 560
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Propagation Delay (tPD) — 12 ns (typ, -1 speed grade)
Global Setup Time (tFSU) — 3.0 ns
Clock-to-Output (tFCO) — 4.8 ns
Maximum Internal Frequency (fCNT) — 145 MHz
Supply Voltage (VCC) — 5.0 V
Operating Temperature (Grade) — -40C to +85C (industrial, "-1O" suffix)
Process Technology — CMOS EEPROM, 0.65 um
Programming — In-system programmable via IEEE 1149.1 JTAG
Architecture — Multiple Array MatriX (MAX), third generation
Packhaging — RQFP-240 (240-pin Reduced-height QFP)
Tindminan RoHS — Compliant (per Altera/Intel product page)
Lead-Free — Yes

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