LCMXO2-1200HC-4TG100C vs LCMXO2-640HC-4TG100C तुलना
विस्तृत दोनों ओर की तुलना LCMXO2-1200HC-4TG100C द्वारा Lattice Semiconductor और LCMXO2-640HC-4TG100C द्वारा Lattice Semiconductor. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Lattice Semiconductor
LCMXO2-1200HC-4TG100C - 1280-LUT 3.3V FPGA | Lattice
LCMXO2-1200HC-4TG100C ✓ सक्रियLattice Semiconductor
LCMXO2-640HC-4TG100C - 640 LUT MachXO2 FPGA, 100-LQFP | Lattice
LCMXO2-640HC-4TG100C ✓ सक्रियविशेषता तुलना
| पैरामीटर | LCMXO2-1200HC-4TG100C | LCMXO2-640HC-4TG100C |
|---|---|---|
| ब्रांड | Lattice Semiconductor | Lattice Semiconductor |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | MachXO2 | — |
| Logic Cells | 1,280 cells | — |
| LUT Count | 1,280 LUTs | — |
| Available I/O | 79 I/O | — |
| User Memory | 256 kbits | — |
| Distributed RAM | Up to 54 kbits | Up to 18.4 kbits (640 LUTs x 32 bits) |
| Dedicated FIFO Control Logic | Supported | — |
| सप्लाई वोल्टेज | 3.3 V | — |
| Speed Grade | -4 | — |
| Technology | Advanced 65 nm low-power process | — |
| Standby Power | As low as 22 uW | As low as 22 µW |
| I/O Feature | Programmable low-swing differential I/O | — |
| Power-Saving Modes | Standby mode and other power-saving options | — |
| ऑपरेटिंग तापमान | 0 C to 85 C junction | 0C to +85C (Commercial, C suffix) |
| पैकेज | TG100, 100-pin TQFP, 14 x 14 mm | 100-pin TQFP (TG100), 14 x 14 mm |
| माउंटिंग प्रकार | Surface Mount | — |
| Voltage Variant | 2.5 V or 3.3 V external VCC supply for HC family | — |
| RoHS | RoHS listed by the Micros product excerpt | — |
| Family | — | MachXO2 |
| Logic Elements / LUTs | — | 640 LUTs (4-input) |
| Number of PLDs (Logic Blocks) | — | 80 |
| Embedded Block RAM (EBR) | — | 18,432 bits (2 x 9 kbit blocks) |
| Number of User I/Os | — | 78 |
| Number of Macrocells | — | 320 |
| Maximum Operating Frequency | — | 136.6 MHz |
| Programmable Type | — | In System Programmable (Flash + SRAM) |
| Core Voltage (Vcc) | — | 3.3 V (typical HC grade) |
| I/O Voltage (Vccio) | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | LVCMOS 1.2-3.3 V, LVDS, LVPECL, programmable differential |
| Process Technology | — | 65 nm low-power CMOS |
| Configuration Memory | — | On-chip Flash (non-volatile) + SRAM |
| Lead-Free / RoHS | — | Lead Free, RoHS Compliant |
| हैलोजन फ्री | — | Yes (per Lattice MachXO2 family datasheet) |