EPM7256AQI208-10 - 256-Macrocell MAX 7000A CPLD, 10ns, PQFP-208 | Intel
MPN: EPM7256AQI208-10 ✗ जीवन की समाप्तिEPM7256AQI208-10 अवलोकन
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the instant-on behavior, deterministic timing, and single-chip simplicity of traditional PAL/GAL architectures with the density and macrocell richness of small FPGAs. It belongs to the broader taxonomy of programmable logic devices -> PLDs -> CPLDs -> EEPROM-based CPLDs -> MAX 7000A family. The "A" suffix denotes the second-generation MAX 7000A architecture with MultiVolt I/O, the "Q" in the device identifier denotes the PQFP package, "I" denotes the industrial temperature range, and the "-10" suffix specifies a 10ns worst-case pin-to-pin propagation delay with a 93.5 MHz maximum internal counter frequency.
Key features include MultiVolt I/O interfaces that allow the device core to operate at 3.3V while I/O banks remain compatible with 5.0V, 3.3V, and 2.5V logic levels; 4.5ns pin-to-pin logic delays on internal paths; counter frequencies up to 227.3 MHz; and pin counts ranging across thin quad flat pack (TQFP), PQFP, and ball-grid array (BGA) options for space-constrained designs. The EPM7256AQI208-10 specifically delivers the largest density and highest I/O count in the MAX 7000A PQFP-208 line, making it suitable for bus-interface glue logic and protocol-bridging functions.
Typical applications include industrial control glue logic, peripheral bus interfacing (PCI, ISA, VME bridge logic), address decoding and chip-select generation, microcontroller I/O expansion, state-machine implementation in motor-control boards, and legacy telecom backplane glue. Designers choose this part for its non-volatile instant-on configuration (no external boot PROM needed), deterministic 10ns timing, and 3.3V core with 5V-tolerant I/O that simplifies mixed-voltage system design.
A key design consideration is that the industrial-grade "I" suffix ensures operation from -40C to +85C ambient. Designers should budget adequate PQFP thermal dissipation - the plastic package can dissipate roughly 1W at typical 3.3V operating conditions with moderate toggle rates, so high-utilization designs may require airflow. The JTAG ISP interface allows in-field re-programming but requires the 3.3V VCCIO rail to be stable during ISP cycles.
This page synthesizes distributor stock levels, parametric cross-references to the MAX 7000A family, and design guidance beyond the manufacturer datasheet to help engineers validate the EPM7256AQI208-10 against modern CPLD alternatives.
के लिए ड्रॉप-इन विकल्प EPM7256AQI208-10 — समान पैकेज, पिन-टू-पिन संगत। PCB रीवर्क आवश्यक करने वाले भिन्न-पैकेज पार्ट्स शामिल नहीं हैं।
इस सीरीज़ के वेरिएंट
समान श्रृंखला के मॉडल जो ड्रॉप-इन संगत हैं EPM7256AQI208-10 (समान फॉर्म फैक्टर और फुटप्रिंट) — इसमें भिन्न Package, RoHS Status, Operating Temperature, Maximum Internal Frequency, User I/O Pins.
EPM7256AQC208-7
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM7256AEQC208-5N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM7256AQC208-10
✅ ड्रॉप-इन ⚠️ विनिर्देश असत्यापित📋 संदर्भ विकल्प (कैटलॉग में नहीं)
EPM7256AEFC256-7
✅ ड्रॉप-इन ⚠️ विनिर्देश असत्यापित📋 संदर्भ विकल्प (कैटलॉग में नहीं)
EPM7256AEQI208-7N
✅ ड्रॉप-इन ⚠️ विनिर्देश असत्यापितकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM3256AQC208-10N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM7256AQI208-10 Maximum Ratings और Electrical Characteristics
| Family | MAX 7000A |
| Macrocells | 256 |
| Logic Array Blocks (LABs) | 16 |
| Usable Gates | 5,000 |
| User I/O Pins | 68 |
| Pin-to-Pin Propagation Delay | 10 ns |
| Maximum Internal Frequency | 93.5 MHz |
| Maximum Counter Frequency | 227.3 MHz |
| Supply Voltage (Core) | 3.3 V |
| I/O Logic Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| पैकेज | PQFP-208 |
| Programmability | EEPROM, in-system via JTAG (IEEE 1149.1) |
| ऑपरेटिंग तापमान | -40C to +85C (industrial) |
| Process Technology | CMOS, EEPROM-based |
| RoHS स्थिति | Compliant (lead-free per distributor data) |
EPM7256AQI208-10 पिन कॉन्फ़िगरेशन
| पिन 1 | I/O — User I/O - bank 1 |
| पिन 2 | I/O — User I/O - bank 1 |
| पिन 3 | I/O — User I/O - bank 1 |
| पिन 4 | I/O — User I/O - bank 1 |
| पिन 5 | I/O — User I/O - bank 1 |
| पिन 6 | GND — Ground |
| पिन 7 | I/O — User I/O - bank 1 |
| पिन 8 | I/O — User I/O - bank 1 |
| पिन 9 | I/O — User I/O - bank 1 |
| पिन 10 | I/O — User I/O - bank 1 |
| पिन 11 | I/O — User I/O - bank 1 |
| पिन 12 | VCCIO1 — I/O bank 1 supply voltage |
| पिन 13 | I/O — User I/O - bank 1 |
| पिन 14 | I/O — User I/O - bank 1 |
| पिन 15 | I/O — User I/O - bank 1 |
| पिन 16 | I/O — User I/O - bank 1 |
| पिन 17 | I/O — User I/O - bank 1 |
| पिन 18 | GND — Ground |
| पिन 19 | I/O — User I/O - bank 1 |
| पिन 20 | I/O — User I/O - bank 1 |
| पिन 21 | I/O — User I/O - bank 1 |
| पिन 22 | I/O — User I/O - bank 1 |
| पिन 23 | I/O — User I/O - bank 1 |
| पिन 24 | VCCIO1 — I/O bank 1 supply voltage |
| पिन 25 | I/O — User I/O - bank 1 |
| पिन 26 | I/O — User I/O - bank 1 |
| पिन 27 | I/O — User I/O - bank 1 |
| पिन 28 | I/O — User I/O - bank 1 |
| पिन 29 | I/O — User I/O - bank 1 |
| पिन 30 | GND — Ground |
| पिन 31 | I/O — User I/O - bank 1 |
| पिन 32 | I/O — User I/O - bank 1 |
| पिन 33 | I/O — User I/O - bank 1 |
| पिन 34 | I/O — User I/O - bank 1 |
| पिन 35 | I/O — User I/O - bank 1 |
| पिन 36 | VCCIO1 — I/O bank 1 supply voltage |
| पिन 37 | I/O — User I/O - bank 1 |
| पिन 38 | I/O — User I/O - bank 1 |
| पिन 39 | I/O — User I/O - bank 1 |
| पिन 40 | I/O — User I/O - bank 1 |
| पिन 41 | I/O — User I/O - bank 1 |
| पिन 42 | GND — Ground |
| पिन 43 | I/O — User I/O - bank 1 |
| पिन 44 | I/O — User I/O - bank 1 |
| पिन 45 | I/O — User I/O - bank 1 |
| पिन 46 | I/O — User I/O - bank 1 |
| पिन 47 | I/O — User I/O - bank 1 |
| पिन 48 | VCCIO1 — I/O bank 1 supply voltage |
| पिन 49 | I/O — User I/O - bank 1 |
| पिन 50 | I/O — User I/O - bank 1 |
| पिन 51 | I/O — User I/O - bank 1 |
| पिन 52 | I/O — User I/O - bank 1 |
| पिन 53 | I/O — User I/O - bank 1 |
| पिन 54 | GND — Ground |
| पिन 55 | I/O — User I/O - bank 2 |
| पिन 56 | I/O — User I/O - bank 2 |
| पिन 57 | I/O — User I/O - bank 2 |
| पिन 58 | I/O — User I/O - bank 2 |
| पिन 59 | I/O — User I/O - bank 2 |
| पिन 60 | VCCIO2 — I/O bank 2 supply voltage |
| पिन 61 | I/O — User I/O - bank 2 |
| पिन 62 | I/O — User I/O - bank 2 |
| पिन 63 | I/O — User I/O - bank 2 |
| पिन 64 | I/O — User I/O - bank 2 |
| पिन 65 | I/O — User I/O - bank 2 |
| पिन 66 | GND — Ground |
| पिन 67 | I/O — User I/O - bank 2 |
| पिन 68 | I/O — User I/O - bank 2 |
| पिन 69 | I/O — User I/O - bank 2 |
| पिन 70 | I/O — User I/O - bank 2 |
| पिन 71 | I/O — User I/O - bank 2 |
| पिन 72 | VCCIO2 — I/O bank 2 supply voltage |
| पिन 73 | I/O — User I/O - bank 2 |
| पिन 74 | I/O — User I/O - bank 2 |
| पिन 75 | I/O — User I/O - bank 2 |
| पिन 76 | I/O — User I/O - bank 2 |
| पिन 77 | I/O — User I/O - bank 2 |
| पिन 78 | GND — Ground |
| पिन 79 | TDI — JTAG Test Data In |
| पिन 80 | TMS — JTAG Test Mode Select |
| पिन 81 | TCK — JTAG Test Clock |
| पिन 82 | VCC — Core supply voltage (3.3V) |
| पिन 83 | TDO — JTAG Test Data Out |
| पिन 84 | GND — Ground |
| पिन 85 | I/O — User I/O - bank 3 |
| पिन 86 | I/O — User I/O - bank 3 |
| पिन 87 | I/O — User I/O - bank 3 |
| पिन 88 | I/O — User I/O - bank 3 |
| पिन 89 | I/O — User I/O - bank 3 |
| पिन 90 | VCCIO3 — I/O bank 3 supply voltage |
| पिन 91 | I/O — User I/O - bank 3 |
| पिन 92 | I/O — User I/O - bank 3 |
| पिन 93 | I/O — User I/O - bank 3 |
| पिन 94 | I/O — User I/O - bank 3 |
| पिन 95 | I/O — User I/O - bank 3 |
| पिन 96 | GND — Ground |
| पिन 97 | I/O — User I/O - bank 3 |
| पिन 98 | I/O — User I/O - bank 3 |
| पिन 99 | I/O — User I/O - bank 3 |
| पिन 100 | I/O — User I/O - bank 3 |
| पिन 101 | I/O — User I/O - bank 3 |
| पिन 102 | VCCIO3 — I/O bank 3 supply voltage |
| पिन 103 | I/O — User I/O - bank 3 |
| पिन 104 | I/O — User I/O - bank 3 |
| पिन 105 | I/O — User I/O - bank 3 |
| पिन 106 | I/O — User I/O - bank 3 |
| पिन 107 | I/O — User I/O - bank 3 |
| पिन 108 | GND — Ground |
| पिन 109 | I/O — User I/O - bank 3 |
| पिन 110 | I/O — User I/O - bank 3 |
| पिन 111 | I/O — User I/O - bank 3 |
| पिन 112 | I/O — User I/O - bank 3 |
| पिन 113 | I/O — User I/O - bank 3 |
| पिन 114 | VCCIO3 — I/O bank 3 supply voltage |
| पिन 115 | I/O — User I/O - bank 3 |
| पिन 116 | I/O — User I/O - bank 3 |
| पिन 117 | I/O — User I/O - bank 3 |
| पिन 118 | I/O — User I/O - bank 3 |
| पिन 119 | I/O — User I/O - bank 3 |
| पिन 120 | GND — Ground |
| पिन 121 | GCLK2 — Global clock input 2 |
| पिन 122 | OE2 — Output enable 2 |
| पिन 123 | I/O — User I/O - bank 4 |
| पिन 124 | I/O — User I/O - bank 4 |
| पिन 125 | I/O — User I/O - bank 4 |
| पिन 126 | I/O — User I/O - bank 4 |
| पिन 127 | I/O — User I/O - bank 4 |
| पिन 128 | VCCIO4 — I/O bank 4 supply voltage |
| पिन 129 | I/O — User I/O - bank 4 |
| पिन 130 | I/O — User I/O - bank 4 |
| पिन 131 | I/O — User I/O - bank 4 |
| पिन 132 | I/O — User I/O - bank 4 |
| पिन 133 | I/O — User I/O - bank 4 |
| पिन 134 | GND — Ground |
| पिन 135 | I/O — User I/O - bank 4 |
| पिन 136 | I/O — User I/O - bank 4 |
| पिन 137 | I/O — User I/O - bank 4 |
| पिन 138 | I/O — User I/O - bank 4 |
| पिन 139 | I/O — User I/O - bank 4 |
| पिन 140 | VCCIO4 — I/O bank 4 supply voltage |
| पिन 141 | I/O — User I/O - bank 4 |
| पिन 142 | I/O — User I/O - bank 4 |
| पिन 143 | I/O — User I/O - bank 4 |
| पिन 144 | I/O — User I/O - bank 4 |
| पिन 145 | I/O — User I/O - bank 4 |
| पिन 146 | GND — Ground |
| पिन 147 | I/O — User I/O - bank 4 |
| पिन 148 | I/O — User I/O - bank 4 |
| पिन 149 | I/O — User I/O - bank 4 |
| पिन 150 | I/O — User I/O - bank 4 |
| पिन 151 | I/O — User I/O - bank 4 |
| पिन 152 | VCCIO4 — I/O bank 4 supply voltage |
| पिन 153 | I/O — User I/O - bank 4 |
| पिन 154 | I/O — User I/O - bank 4 |
| पिन 155 | I/O — User I/O - bank 4 |
| पिन 156 | I/O — User I/O - bank 4 |
| पिन 157 | I/O — User I/O - bank 4 |
| पिन 158 | GND — Ground |
| पिन 159 | I/O — User I/O - bank 4 |
| पिन 160 | I/O — User I/O - bank 4 |
| पिन 161 | I/O — User I/O - bank 4 |
| पिन 162 | I/O — User I/O - bank 4 |
| पिन 163 | I/O — User I/O - bank 4 |
| पिन 164 | VCCIO4 — I/O bank 4 supply voltage |
| पिन 165 | I/O — User I/O - bank 4 |
| पिन 166 | I/O — User I/O - bank 4 |
| पिन 167 | I/O — User I/O - bank 4 |
| पिन 168 | I/O — User I/O - bank 4 |
| पिन 169 | I/O — User I/O - bank 4 |
| पिन 170 | GND — Ground |
| पिन 171 | I/O — User I/O - bank 4 |
| पिन 172 | I/O — User I/O - bank 4 |
| पिन 173 | I/O — User I/O - bank 4 |
| पिन 174 | I/O — User I/O - bank 4 |
| पिन 175 | I/O — User I/O - bank 4 |
| पिन 176 | VCCIO4 — I/O bank 4 supply voltage |
| पिन 177 | I/O — User I/O - bank 4 |
| पिन 178 | I/O — User I/O - bank 4 |
| पिन 179 | I/O — User I/O - bank 4 |
| पिन 180 | I/O — User I/O - bank 4 |
| पिन 181 | I/O — User I/O - bank 4 |
| पिन 182 | GND — Ground |
| पिन 183 | GCLK1 — Global clock input 1 |
| पिन 184 | OE1 — Output enable 1 |
| पिन 185 | I/O — User I/O - bank 1 |
| पिन 186 | I/O — User I/O - bank 1 |
| पिन 187 | I/O — User I/O - bank 1 |
| पिन 188 | I/O — User I/O - bank 1 |
| पिन 189 | I/O — User I/O - bank 1 |
| पिन 190 | VCCIO1 — I/O bank 1 supply voltage |
| पिन 191 | I/O — User I/O - bank 1 |
| पिन 192 | I/O — User I/O - bank 1 |
| पिन 193 | I/O — User I/O - bank 1 |
| पिन 194 | I/O — User I/O - bank 1 |
| पिन 195 | I/O — User I/O - bank 1 |
| पिन 196 | GND — Ground |
| पिन 197 | I/O — User I/O - bank 1 |
| पिन 198 | I/O — User I/O - bank 1 |
| पिन 199 | I/O — User I/O - bank 1 |
| पिन 200 | I/O — User I/O - bank 1 |
| पिन 201 | I/O — User I/O - bank 1 |
| पिन 202 | VCCIO1 — I/O bank 1 supply voltage |
| पिन 203 | I/O — User I/O - bank 1 |
| पिन 204 | I/O — User I/O - bank 1 |
| पिन 205 | I/O — User I/O - bank 1 |
| पिन 206 | I/O — User I/O - bank 1 |
| पिन 207 | I/O — User I/O - bank 1 |
| पिन 208 | GND — Ground |
सामान्य अनुप्रयोग
EPM7256AQI208-10 के लिए उपयुक्त है 6 अनुप्रयोगs: Industrial Control Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip-Select Generation, Motor Control State Machines, Legacy Telecom Backplane Glue Logic, Microcontroller I/O Expansion.
Industrial Control Glue Logic
The EPM7256AQI208-10's 256 macrocells and 68 I/O pins make it ideal for industrial control boards where deterministic 10ns timing and instant-on EEPROM configuration are required. Its MultiVolt I/O lets it interface to legacy 5V sensors and 3.3V microcontrollers on the same PCB without level shifters. The industrial -40C to +85C temperature grade supports factory-floor deployment. With 227.3 MHz counter frequency, it can drive high-speed encoder and PWM control loops while the JTAG ISP interface enables in-field firmware updates during commissioning.
अनुशंसित
Peripheral Bus Interface Bridging
The 68 user I/O pins of the EPM7256AQI208-10 enable direct bridging between legacy peripheral buses (ISA, VME, PC/104) and modern 3.3V processor buses, eliminating the need for multiple discrete glue-logic chips. Its 10ns pin-to-pin delay ensures deterministic bus-arbitration and chip-select generation timing across the full industrial temperature range. The non-volatile EEPROM configuration means no boot-PROM is required, reducing BOM cost and board footprint in embedded computing designs.
अनुशंसित
Address Decoding and Chip-Select Generation
The EPM7256AQI208-10 is well suited to generating chip-select signals for memory-mapped peripherals in 16-bit and 32-bit embedded systems, with 256 macrocells providing ample capacity for complex address maps. Its 10ns propagation delay matches the access-time budgets of most SRAM, Flash, and peripheral devices used in industrial controllers. The MultiVolt I/O permits direct interface to 5V memory banks from a 3.3V processor without external buffers, simplifying board layout.
अनुशंसित
Motor Control State Machines
The EPM7256AQI208-10's deterministic timing and 227.3 MHz internal counter frequency enable precise PWM and stepper-motor state-machine implementation in industrial motor-control applications. Its 68 I/O pins easily accommodate multi-axis encoder inputs, Hall-sensor feedback, and PWM outputs for 3-phase inverter control. The industrial temperature range supports under-hood and factory-cabinet environments where ambient temperatures can exceed 70C during operation.
अनुशंसित
Legacy Telecom Backplane Glue Logic
Telecom backplanes often require 5V-tolerant I/O and deterministic timing for TDM bus arbitration and clock-distribution functions - exactly the role the EPM7256AQI208-10 was designed for. Its 256 macrocells handle full backplane address decoding while 68 I/O pins support multiple TDM framers and serializers. The JTAG ISP interface allows board-level diagnostics without removing the part, critical for high-availability telecom infrastructure.
अनुशंसित
Microcontroller I/O Expansion
The EPM7256AQI208-10 can serve as a high-density I/O expander for microcontrollers that lack sufficient GPIO pins, providing 68 additional user I/O with deterministic read/write timing. The JTAG interface allows firmware updates without reprogramming the host microcontroller, simplifying field maintenance. MultiVolt I/O enables direct interface to 5V microcontrollers or 3.3V ARM Cortex-M devices on the same board.
अनुशंसित
अनुशंसित उत्पादों का सारांश
के लिए इंजीनियरिंग संदर्भ डेटा EPM7256AQI208-10 — तुलना, डिज़ाइन मार्गदर्शन और अनुपालन जानकारी।
चयन गाइड
विकल्पों के साथ तुलना
| पैरामीटर | यह उत्पाद | EPM7256AQC208-7 | EPM7256AEQC208-5N | EPM3256AQC208-10N | EPM7256AEQI208-7N |
|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 (same) | PQFP-208 (same) | PQFP-208 (same) | PQFP-208 (same) |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Pin-to-Pin Delay | 10 ns | 7 ns (-30%) | 5 ns (-50%) | 10 ns (same) | 7 ns (-30%) |
| Macrocells | 256 | 256 (same) | 256 (same) | 256 (same) | 256 (same) |
| User I/O Pins | 68 | 68 (same) | 68 (same) | 68 (same) | 68 (same) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Maximum Counter Frequency | 227.3 MHz | 285.7 MHz | 333.3 MHz | 227.3 MHz | 285.7 MHz |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
| Family | MAX 7000A | MAX 7000A | MAX 7000AE | MAX 3000A | MAX 7000AE |
मुख्य विशेषताएँ
- Industrial temperature range with full -40C to +85C operation (बनामEPM7256AQC208-7)
- Largest macrocell density in MAX 7000A PQFP-208 line (बनामEPM7256AETI144-7N)
- MultiVolt I/O for 5V/3.3V/2.5V mixed-voltage interfacing (बनामEPM3256AQC208-10N)
डिज़ाइन नोट्स
The EPM7256AQI208-10 requires a stable 3.3V core supply (VCC) and four independent I/O bank supplies (VCCIO1-VCCIO4) which may be set to 2.5V, 3.3V, or 5.0V depending on the logic family being interfaced. Decoupling: place one 0.1uF ceramic capacitor near each VCC and VCCIO pin, plus a bulk 10-100uF tantalum or polymer capacitor at the board's power entry. Estimated: with 68 I/O toggling at 10 MHz and 50% utilization, I/O current draw is approximately 100-200 mA on the VCCIO rails; budget the 3.3V regulator accordingly. During JTAG ISP, all VCCIO rails must remain stable to prevent programming errors.
The PQFP-208 plastic package has a typical theta-JA of approximately 25-35 C/W depending on PCB copper area. Estimated: at 100 mA I/O current with all banks driving 5V outputs into 50pF loads at 10 MHz, internal dissipation can reach 0.5-1.0W, producing a 12-35C junction-temperature rise above ambient at room temperature. For full industrial -40C to +85C operation, ensure the design includes at least 4 square inches of ground-plane copper under the PQFP to keep junction temperatures within spec. Avoid placing the CPLD near board-edge heat sinks or other high-power devices.
Place the EPM7256AQI208-10 close to its associated microcontrollers or bus devices to minimize signal-trace lengths; keep high-speed GCLK traces under 25mm to avoid reflections. Use controlled-impedance routing (typically 50-ohm microstrip or stripline) for GCLK1, GCLK2, and any clock-distribution outputs above 50 MHz. Separate analog and digital ground planes if mixing 5V analog signals into the I/O banks, joining them only at a single star-point near the CPLD's GND pins. Reserve JTAG pins (TDI, TMS, TCK, TDO) on a dedicated header or test pad for in-system programming access.
Do not exceed the absolute-maximum VCCIO voltage of 5.5V on any I/O bank or the part may suffer permanent damage. Note that the 10ns pin-to-pin delay is the worst-case over the full industrial temperature range; designs targeting the highest commercial-temperature timing margins should specify the 7ns -7 speed grade (EPM7256AQC208-7). When migrating from commercial-grade MAX 7000A parts, ensure the new device's MultiVolt I/O bank voltages match the legacy circuit - the 'E' suffix variants (e.g., EPM7256AEQC208-5N) have enhanced MultiVolt features that differ subtly from the non-'E' parts. Always confirm pinout compatibility before substituting between PQFP-208 and FineLine BGA packages.
अनुपालन जानकारी
RoHS-compliant per distributor listings (Altera-Price.com confirms lead-free / RoHS status). AEC-Q100 automotive qualification not specified - this is an industrial-grade part. REACH and halogen-free status not explicitly stated in verified data; consult Intel product declaration for confirmation.
