EPM7256AQI208-10 - 256-Macrocell MAX 7000A CPLD, 10ns, PQFP-208 | Intel
MPN: EPM7256AQI208-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $13.22 | $13.22 |
| 10 | $22.61 | $226.10 |
| 100 | $22.61 | $2,261.00 |
| 500 | $22.61 | $11,305.00 |
| 1,000 | $22.61 | $22,610.00 |
Drop-in alternatives for EPM7256AQI208-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM7256AQI208-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Macrocells | 256 |
| Logic Array Blocks (LABs) | 16 |
| Usable Gates | 5,000 |
| User I/O Pins | 68 |
| Pin-to-Pin Propagation Delay | 10 ns |
| Maximum Internal Frequency | 93.5 MHz |
| Maximum Counter Frequency | 227.3 MHz |
| Supply Voltage (Core) | 3.3 V |
| I/O Logic Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| Package | PQFP-208 |
| Programmability | EEPROM, in-system via JTAG (IEEE 1149.1) |
| Operating Temperature | -40C to +85C (industrial) |
| Process Technology | CMOS, EEPROM-based |
| RoHS Status | Compliant (lead-free per distributor data) |
EPM7256AQI208-10 Pin Configuration
| Pin 1 | I/O — User I/O - bank 1 |
| Pin 2 | I/O — User I/O - bank 1 |
| Pin 3 | I/O — User I/O - bank 1 |
| Pin 4 | I/O — User I/O - bank 1 |
| Pin 5 | I/O — User I/O - bank 1 |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — User I/O - bank 1 |
| Pin 8 | I/O — User I/O - bank 1 |
| Pin 9 | I/O — User I/O - bank 1 |
| Pin 10 | I/O — User I/O - bank 1 |
| Pin 11 | I/O — User I/O - bank 1 |
| Pin 12 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 13 | I/O — User I/O - bank 1 |
| Pin 14 | I/O — User I/O - bank 1 |
| Pin 15 | I/O — User I/O - bank 1 |
| Pin 16 | I/O — User I/O - bank 1 |
| Pin 17 | I/O — User I/O - bank 1 |
| Pin 18 | GND — Ground |
| Pin 19 | I/O — User I/O - bank 1 |
| Pin 20 | I/O — User I/O - bank 1 |
| Pin 21 | I/O — User I/O - bank 1 |
| Pin 22 | I/O — User I/O - bank 1 |
| Pin 23 | I/O — User I/O - bank 1 |
| Pin 24 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 25 | I/O — User I/O - bank 1 |
| Pin 26 | I/O — User I/O - bank 1 |
| Pin 27 | I/O — User I/O - bank 1 |
| Pin 28 | I/O — User I/O - bank 1 |
| Pin 29 | I/O — User I/O - bank 1 |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — User I/O - bank 1 |
| Pin 32 | I/O — User I/O - bank 1 |
| Pin 33 | I/O — User I/O - bank 1 |
| Pin 34 | I/O — User I/O - bank 1 |
| Pin 35 | I/O — User I/O - bank 1 |
| Pin 36 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 37 | I/O — User I/O - bank 1 |
| Pin 38 | I/O — User I/O - bank 1 |
| Pin 39 | I/O — User I/O - bank 1 |
| Pin 40 | I/O — User I/O - bank 1 |
| Pin 41 | I/O — User I/O - bank 1 |
| Pin 42 | GND — Ground |
| Pin 43 | I/O — User I/O - bank 1 |
| Pin 44 | I/O — User I/O - bank 1 |
| Pin 45 | I/O — User I/O - bank 1 |
| Pin 46 | I/O — User I/O - bank 1 |
| Pin 47 | I/O — User I/O - bank 1 |
| Pin 48 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 49 | I/O — User I/O - bank 1 |
| Pin 50 | I/O — User I/O - bank 1 |
| Pin 51 | I/O — User I/O - bank 1 |
| Pin 52 | I/O — User I/O - bank 1 |
| Pin 53 | I/O — User I/O - bank 1 |
| Pin 54 | GND — Ground |
| Pin 55 | I/O — User I/O - bank 2 |
| Pin 56 | I/O — User I/O - bank 2 |
| Pin 57 | I/O — User I/O - bank 2 |
| Pin 58 | I/O — User I/O - bank 2 |
| Pin 59 | I/O — User I/O - bank 2 |
| Pin 60 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 61 | I/O — User I/O - bank 2 |
| Pin 62 | I/O — User I/O - bank 2 |
| Pin 63 | I/O — User I/O - bank 2 |
| Pin 64 | I/O — User I/O - bank 2 |
| Pin 65 | I/O — User I/O - bank 2 |
| Pin 66 | GND — Ground |
| Pin 67 | I/O — User I/O - bank 2 |
| Pin 68 | I/O — User I/O - bank 2 |
| Pin 69 | I/O — User I/O - bank 2 |
| Pin 70 | I/O — User I/O - bank 2 |
| Pin 71 | I/O — User I/O - bank 2 |
| Pin 72 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 73 | I/O — User I/O - bank 2 |
| Pin 74 | I/O — User I/O - bank 2 |
| Pin 75 | I/O — User I/O - bank 2 |
| Pin 76 | I/O — User I/O - bank 2 |
| Pin 77 | I/O — User I/O - bank 2 |
| Pin 78 | GND — Ground |
| Pin 79 | TDI — JTAG Test Data In |
| Pin 80 | TMS — JTAG Test Mode Select |
| Pin 81 | TCK — JTAG Test Clock |
| Pin 82 | VCC — Core supply voltage (3.3V) |
| Pin 83 | TDO — JTAG Test Data Out |
| Pin 84 | GND — Ground |
| Pin 85 | I/O — User I/O - bank 3 |
| Pin 86 | I/O — User I/O - bank 3 |
| Pin 87 | I/O — User I/O - bank 3 |
| Pin 88 | I/O — User I/O - bank 3 |
| Pin 89 | I/O — User I/O - bank 3 |
| Pin 90 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 91 | I/O — User I/O - bank 3 |
| Pin 92 | I/O — User I/O - bank 3 |
| Pin 93 | I/O — User I/O - bank 3 |
| Pin 94 | I/O — User I/O - bank 3 |
| Pin 95 | I/O — User I/O - bank 3 |
| Pin 96 | GND — Ground |
| Pin 97 | I/O — User I/O - bank 3 |
| Pin 98 | I/O — User I/O - bank 3 |
| Pin 99 | I/O — User I/O - bank 3 |
| Pin 100 | I/O — User I/O - bank 3 |
| Pin 101 | I/O — User I/O - bank 3 |
| Pin 102 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 103 | I/O — User I/O - bank 3 |
| Pin 104 | I/O — User I/O - bank 3 |
| Pin 105 | I/O — User I/O - bank 3 |
| Pin 106 | I/O — User I/O - bank 3 |
| Pin 107 | I/O — User I/O - bank 3 |
| Pin 108 | GND — Ground |
| Pin 109 | I/O — User I/O - bank 3 |
| Pin 110 | I/O — User I/O - bank 3 |
| Pin 111 | I/O — User I/O - bank 3 |
| Pin 112 | I/O — User I/O - bank 3 |
| Pin 113 | I/O — User I/O - bank 3 |
| Pin 114 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 115 | I/O — User I/O - bank 3 |
| Pin 116 | I/O — User I/O - bank 3 |
| Pin 117 | I/O — User I/O - bank 3 |
| Pin 118 | I/O — User I/O - bank 3 |
| Pin 119 | I/O — User I/O - bank 3 |
| Pin 120 | GND — Ground |
| Pin 121 | GCLK2 — Global clock input 2 |
| Pin 122 | OE2 — Output enable 2 |
| Pin 123 | I/O — User I/O - bank 4 |
| Pin 124 | I/O — User I/O - bank 4 |
| Pin 125 | I/O — User I/O - bank 4 |
| Pin 126 | I/O — User I/O - bank 4 |
| Pin 127 | I/O — User I/O - bank 4 |
| Pin 128 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 129 | I/O — User I/O - bank 4 |
| Pin 130 | I/O — User I/O - bank 4 |
| Pin 131 | I/O — User I/O - bank 4 |
| Pin 132 | I/O — User I/O - bank 4 |
| Pin 133 | I/O — User I/O - bank 4 |
| Pin 134 | GND — Ground |
| Pin 135 | I/O — User I/O - bank 4 |
| Pin 136 | I/O — User I/O - bank 4 |
| Pin 137 | I/O — User I/O - bank 4 |
| Pin 138 | I/O — User I/O - bank 4 |
| Pin 139 | I/O — User I/O - bank 4 |
| Pin 140 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 141 | I/O — User I/O - bank 4 |
| Pin 142 | I/O — User I/O - bank 4 |
| Pin 143 | I/O — User I/O - bank 4 |
| Pin 144 | I/O — User I/O - bank 4 |
| Pin 145 | I/O — User I/O - bank 4 |
| Pin 146 | GND — Ground |
| Pin 147 | I/O — User I/O - bank 4 |
| Pin 148 | I/O — User I/O - bank 4 |
| Pin 149 | I/O — User I/O - bank 4 |
| Pin 150 | I/O — User I/O - bank 4 |
| Pin 151 | I/O — User I/O - bank 4 |
| Pin 152 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 153 | I/O — User I/O - bank 4 |
| Pin 154 | I/O — User I/O - bank 4 |
| Pin 155 | I/O — User I/O - bank 4 |
| Pin 156 | I/O — User I/O - bank 4 |
| Pin 157 | I/O — User I/O - bank 4 |
| Pin 158 | GND — Ground |
| Pin 159 | I/O — User I/O - bank 4 |
| Pin 160 | I/O — User I/O - bank 4 |
| Pin 161 | I/O — User I/O - bank 4 |
| Pin 162 | I/O — User I/O - bank 4 |
| Pin 163 | I/O — User I/O - bank 4 |
| Pin 164 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 165 | I/O — User I/O - bank 4 |
| Pin 166 | I/O — User I/O - bank 4 |
| Pin 167 | I/O — User I/O - bank 4 |
| Pin 168 | I/O — User I/O - bank 4 |
| Pin 169 | I/O — User I/O - bank 4 |
| Pin 170 | GND — Ground |
| Pin 171 | I/O — User I/O - bank 4 |
| Pin 172 | I/O — User I/O - bank 4 |
| Pin 173 | I/O — User I/O - bank 4 |
| Pin 174 | I/O — User I/O - bank 4 |
| Pin 175 | I/O — User I/O - bank 4 |
| Pin 176 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 177 | I/O — User I/O - bank 4 |
| Pin 178 | I/O — User I/O - bank 4 |
| Pin 179 | I/O — User I/O - bank 4 |
| Pin 180 | I/O — User I/O - bank 4 |
| Pin 181 | I/O — User I/O - bank 4 |
| Pin 182 | GND — Ground |
| Pin 183 | GCLK1 — Global clock input 1 |
| Pin 184 | OE1 — Output enable 1 |
| Pin 185 | I/O — User I/O - bank 1 |
| Pin 186 | I/O — User I/O - bank 1 |
| Pin 187 | I/O — User I/O - bank 1 |
| Pin 188 | I/O — User I/O - bank 1 |
| Pin 189 | I/O — User I/O - bank 1 |
| Pin 190 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 191 | I/O — User I/O - bank 1 |
| Pin 192 | I/O — User I/O - bank 1 |
| Pin 193 | I/O — User I/O - bank 1 |
| Pin 194 | I/O — User I/O - bank 1 |
| Pin 195 | I/O — User I/O - bank 1 |
| Pin 196 | GND — Ground |
| Pin 197 | I/O — User I/O - bank 1 |
| Pin 198 | I/O — User I/O - bank 1 |
| Pin 199 | I/O — User I/O - bank 1 |
| Pin 200 | I/O — User I/O - bank 1 |
| Pin 201 | I/O — User I/O - bank 1 |
| Pin 202 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 203 | I/O — User I/O - bank 1 |
| Pin 204 | I/O — User I/O - bank 1 |
| Pin 205 | I/O — User I/O - bank 1 |
| Pin 206 | I/O — User I/O - bank 1 |
| Pin 207 | I/O — User I/O - bank 1 |
| Pin 208 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256AQI208-10 is suitable for 6 applications: Industrial Control Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip-Select Generation, Motor Control State Machines, Legacy Telecom Backplane Glue Logic, Microcontroller I/O Expansion.
Industrial Control Glue Logic
The EPM7256AQI208-10's 256 macrocells and 68 I/O pins make it ideal for industrial control boards where deterministic 10ns timing and instant-on EEPROM configuration are required. Its MultiVolt I/O lets it interface to legacy 5V sensors and 3.3V microcontrollers on the same PCB without level shifters. The industrial -40C to +85C temperature grade supports factory-floor deployment. With 227.3 MHz counter frequency, it can drive high-speed encoder and PWM control loops while the JTAG ISP interface enables in-field firmware updates during commissioning.
Recommended
Peripheral Bus Interface Bridging
The 68 user I/O pins of the EPM7256AQI208-10 enable direct bridging between legacy peripheral buses (ISA, VME, PC/104) and modern 3.3V processor buses, eliminating the need for multiple discrete glue-logic chips. Its 10ns pin-to-pin delay ensures deterministic bus-arbitration and chip-select generation timing across the full industrial temperature range. The non-volatile EEPROM configuration means no boot-PROM is required, reducing BOM cost and board footprint in embedded computing designs.
Recommended
Address Decoding and Chip-Select Generation
The EPM7256AQI208-10 is well suited to generating chip-select signals for memory-mapped peripherals in 16-bit and 32-bit embedded systems, with 256 macrocells providing ample capacity for complex address maps. Its 10ns propagation delay matches the access-time budgets of most SRAM, Flash, and peripheral devices used in industrial controllers. The MultiVolt I/O permits direct interface to 5V memory banks from a 3.3V processor without external buffers, simplifying board layout.
Recommended
Motor Control State Machines
The EPM7256AQI208-10's deterministic timing and 227.3 MHz internal counter frequency enable precise PWM and stepper-motor state-machine implementation in industrial motor-control applications. Its 68 I/O pins easily accommodate multi-axis encoder inputs, Hall-sensor feedback, and PWM outputs for 3-phase inverter control. The industrial temperature range supports under-hood and factory-cabinet environments where ambient temperatures can exceed 70C during operation.
Recommended
Legacy Telecom Backplane Glue Logic
Telecom backplanes often require 5V-tolerant I/O and deterministic timing for TDM bus arbitration and clock-distribution functions - exactly the role the EPM7256AQI208-10 was designed for. Its 256 macrocells handle full backplane address decoding while 68 I/O pins support multiple TDM framers and serializers. The JTAG ISP interface allows board-level diagnostics without removing the part, critical for high-availability telecom infrastructure.
Recommended
Microcontroller I/O Expansion
The EPM7256AQI208-10 can serve as a high-density I/O expander for microcontrollers that lack sufficient GPIO pins, providing 68 additional user I/O with deterministic read/write timing. The JTAG interface allows firmware updates without reprogramming the host microcontroller, simplifying field maintenance. MultiVolt I/O enables direct interface to 5V microcontrollers or 3.3V ARM Cortex-M devices on the same board.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256AQI208-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256AQC208-7 | EPM7256AEQC208-5N | EPM3256AQC208-10N | EPM7256AEQI208-7N |
|---|---|---|---|---|---|
| Package | PQFP-208 | PQFP-208 (same) | PQFP-208 (same) | PQFP-208 (same) | PQFP-208 (same) |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Pin-to-Pin Delay | 10 ns | 7 ns (-30%) | 5 ns (-50%) | 10 ns (same) | 7 ns (-30%) |
| Macrocells | 256 | 256 (same) | 256 (same) | 256 (same) | 256 (same) |
| User I/O Pins | 68 | 68 (same) | 68 (same) | 68 (same) | 68 (same) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Maximum Counter Frequency | 227.3 MHz | 285.7 MHz | 333.3 MHz | 227.3 MHz | 285.7 MHz |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
| Family | MAX 7000A | MAX 7000A | MAX 7000AE | MAX 3000A | MAX 7000AE |
Key Differentiators
- Industrial temperature range with full -40C to +85C operation (vs EPM7256AQC208-7)
- Largest macrocell density in MAX 7000A PQFP-208 line (vs EPM7256AETI144-7N)
- MultiVolt I/O for 5V/3.3V/2.5V mixed-voltage interfacing (vs EPM3256AQC208-10N)
Design Notes
The EPM7256AQI208-10 requires a stable 3.3V core supply (VCC) and four independent I/O bank supplies (VCCIO1-VCCIO4) which may be set to 2.5V, 3.3V, or 5.0V depending on the logic family being interfaced. Decoupling: place one 0.1uF ceramic capacitor near each VCC and VCCIO pin, plus a bulk 10-100uF tantalum or polymer capacitor at the board's power entry. Estimated: with 68 I/O toggling at 10 MHz and 50% utilization, I/O current draw is approximately 100-200 mA on the VCCIO rails; budget the 3.3V regulator accordingly. During JTAG ISP, all VCCIO rails must remain stable to prevent programming errors.
The PQFP-208 plastic package has a typical theta-JA of approximately 25-35 C/W depending on PCB copper area. Estimated: at 100 mA I/O current with all banks driving 5V outputs into 50pF loads at 10 MHz, internal dissipation can reach 0.5-1.0W, producing a 12-35C junction-temperature rise above ambient at room temperature. For full industrial -40C to +85C operation, ensure the design includes at least 4 square inches of ground-plane copper under the PQFP to keep junction temperatures within spec. Avoid placing the CPLD near board-edge heat sinks or other high-power devices.
Place the EPM7256AQI208-10 close to its associated microcontrollers or bus devices to minimize signal-trace lengths; keep high-speed GCLK traces under 25mm to avoid reflections. Use controlled-impedance routing (typically 50-ohm microstrip or stripline) for GCLK1, GCLK2, and any clock-distribution outputs above 50 MHz. Separate analog and digital ground planes if mixing 5V analog signals into the I/O banks, joining them only at a single star-point near the CPLD's GND pins. Reserve JTAG pins (TDI, TMS, TCK, TDO) on a dedicated header or test pad for in-system programming access.
Do not exceed the absolute-maximum VCCIO voltage of 5.5V on any I/O bank or the part may suffer permanent damage. Note that the 10ns pin-to-pin delay is the worst-case over the full industrial temperature range; designs targeting the highest commercial-temperature timing margins should specify the 7ns -7 speed grade (EPM7256AQC208-7). When migrating from commercial-grade MAX 7000A parts, ensure the new device's MultiVolt I/O bank voltages match the legacy circuit - the 'E' suffix variants (e.g., EPM7256AEQC208-5N) have enhanced MultiVolt features that differ subtly from the non-'E' parts. Always confirm pinout compatibility before substituting between PQFP-208 and FineLine BGA packages.
Compliance Information
RoHS-compliant per distributor listings (Altera-Price.com confirms lead-free / RoHS status). AEC-Q100 automotive qualification not specified - this is an industrial-grade part. REACH and halogen-free status not explicitly stated in verified data; consult Intel product declaration for confirmation.
