Altera

EPM7256AQC208-7 - MAX 7000A CPLD 256 Macrocells | Altera

MPN: EPM7256AQC208-7 βœ— End of Life
In Stock Ships in 1-3 business days
3.0 V to 3.6 V Vdss 208-Pin PQFP (28 x 28 mm) Package 125 MHz Speed EEPROM (non-volatile) Memory
From $27.2 USD / Unit
MOQ: 1 |
Price updated: 2026-09-12
Volume Pricing
Qty Unit Price Extended
1 $42.5 $42.50
10 $38.25 $382.50
100 $34 $3,400.00
500 $30.6 $15,300.00
1,000 $27.2 $27,200.00
ℹ️ All prices are in USD

Drop-in alternatives for EPM7256AQC208-7 β€” same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool β€” Select alternative parts for side-by-side comparison:

EPM7256AQC208-7N

βœ… Drop-In
πŸ“¦ 208-PQFP (28x28)
lead-free (Pb-free) construction, identical 7 ns speed grade and 256 macrocells, pin-to-pin compatible

πŸ“‹ Reference alternative (not in catalog)

EPM7256AQC208-10

βœ… Drop-In ⚠️ 参数待ιͺŒθ―
πŸ“¦ 208-PQFP (28x28)
tPD 10 ns vs 7 ns (+43%), counter frequency ~100 MHz vs 125 MHz (-20%), otherwise pin-to-pin

πŸ“‹ Reference alternative (not in catalog)

EPM7256AQC208-10N

βœ… Drop-In ⚠️ 参数待ιͺŒθ―
πŸ“¦ 208-PQFP (28x28)
lead-free variant of the 10 ns grade; tPD 10 ns vs 7 ns (+43%), same 256 macrocells and 208-pin PQFP

πŸ“‹ Reference alternative (not in catalog)

EPM7256AQC208-5

βœ… Drop-In ⚠️ 参数待ιͺŒθ―
πŸ“¦ 208-PQFP (28x28)
faster 5 ns tPD vs 7 ns (-29%), same 256 macrocells and 208-pin PQFP footprint

πŸ“‹ Reference alternative (not in catalog)

EPM7256AQC208-15

βœ… Drop-In ⚠️ 参数待ιͺŒθ―
πŸ“¦ 208-PQFP (28x28)
slower 15 ns tPD vs 7 ns (+114%), counter frequency ~83 MHz vs 125 MHz (-34%), same package and macrocell count

πŸ“‹ Reference alternative (not in catalog)

EPM7256AEQC208-7N

βœ… Drop-In
πŸ“¦ 208-PQFP (28x28)
MAX 7000AE low-voltage variant, 7 ns speed grade, lead-free, same 208-pin PQFP footprint

πŸ“‹ Reference alternative (not in catalog)

EPM7256AQC208-7 Maximum Ratings & Electrical Characteristics

Family MAX 7000A
Programmable Type In System Programmable (ISP), EEPROM-based
Macrocells 256
Usable Gates 5,000
Logic Array Blocks (LABs) 16
Maximum User I/O Pins 164
Pin-to-Pin Logic Delay (tPD) 7 ns
Maximum Counter Frequency 125 MHz
Internal Toggle Frequency 227.3 MHz
Supply Voltage - Internal 3.0 V to 3.6 V
I/O Voltage Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O)
Package 208-Pin PQFP (28 x 28 mm)
Supplier Device Package 208-PQFP (28x28)
Mounting Type Surface Mount
Operating Temperature Range 0C to +70C (commercial)
JTAG Interface IEEE 1149.1 (JTAG) boundary scan
Configuration Memory EEPROM (non-volatile)
Speed Grade -7

EPM7256AQC208-7 Pin Configuration

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pin 1 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 2 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 3 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 4 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 5 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 6 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 7 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 8 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 9 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 10 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 11 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 12 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 13 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 14 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 15 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 16 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 17 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 18 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 19 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 20 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 21 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 22 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 23 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 24 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 25 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 26 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 27 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 28 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 29 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 30 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 31 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 32 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 33 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 34 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 35 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 36 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 37 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 38 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 39 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 40 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 41 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 42 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 43 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 44 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 45 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 46 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 47 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 48 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 49 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 50 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 51 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 52 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 53 GND β€” Ground
Pin 54 VCCINT β€” Internal 3.3 V core supply
Pin 55 GND β€” Ground
Pin 56 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 57 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 58 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 59 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 60 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 61 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 62 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 63 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 64 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 65 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 66 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 67 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 68 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 69 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 70 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 71 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 72 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 73 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 74 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 75 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 76 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 77 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 78 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 79 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 80 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 81 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 82 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 83 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 84 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 85 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 86 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 87 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 88 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 89 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 90 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 91 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 92 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 93 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 94 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 95 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 96 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 97 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 98 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 99 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 100 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 101 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 102 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 103 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 104 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 105 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 106 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 107 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 108 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 109 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 110 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 111 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 112 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 113 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 114 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 115 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 116 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 117 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 118 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 119 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 120 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 121 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 122 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 123 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 124 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 125 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 126 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 127 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 128 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 129 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 130 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 131 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 132 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 133 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 134 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 135 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 136 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 137 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 138 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 139 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 140 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 141 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 142 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 143 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 144 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 145 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 146 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 147 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 148 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 149 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 150 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 151 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 152 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 153 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 154 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 155 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 156 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 157 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 158 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 159 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 160 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 161 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 162 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 163 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 164 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 165 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 166 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 167 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 168 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 169 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 170 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 171 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 172 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 173 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 174 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 175 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 176 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 177 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 178 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 179 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 180 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 181 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 182 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 183 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 184 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 185 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 186 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 187 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 188 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 189 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 190 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 191 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 192 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 193 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 194 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 195 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 196 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 197 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 198 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 199 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 200 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 201 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 202 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 203 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 204 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 205 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 206 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 207 I/O β€” General-purpose user I/O (MultiVolt compatible)
Pin 208 I/O β€” General-purpose user I/O (MultiVolt compatible)

Safe Operating Area (SOA) & Thermal Characteristics

Safe Operating Area Chart Default safe operating area chart for EPM7256AQC208-7 Drain-to-Source Voltage (Vds) Drain Current (Id)

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPM7256AQC208-7 is suitable for 6 applications: Industrial Control and Factory Automation, Legacy PCI and ISA Bus Bridging, Telecommunications Line-Card Control, Test and Measurement Instrumentation, Lighting Control Systems, Military and Aerospace Legacy Retrofit.

🏭

Industrial Control and Factory Automation

The EPM7256AQC208-7 fits industrial control designs because its 164 user I/O pins and 256 macrocells can absorb the address decoding, chip-select generation, and handshake logic that would otherwise require dozens of discrete 74-series devices. Its 3.0-3.6 V core with MultiVolt I/O tolerates 5.0 V, 3.3 V, and 2.5 V peripherals on the same board, simplifying mixed-voltage retrofits. Because configuration is stored in non-volatile EEPROM, the CPLD is active within microseconds of power-up, which matters for machine-safety interlocks that cannot wait for an external boot PROM. A typical implementation places the device between a host microcontroller and motor-driver or relay-driver stages, where its 7 ns pin-to-pin delay keeps interlock response deterministic. The trade-off is static power: EEPROM-based MAX 7000A devices draw more quiescent current than modern flash CPLDs, so thermal budgeting should account for the 208-pin PQFP package dissipation.

πŸ–₯️

Legacy PCI and ISA Bus Bridging

The EPM7256AQC208-7 is commonly used to bridge legacy PCI and ISA buses to modern peripherals because its 7 ns pin-to-pin delay and 125 MHz counter frequency provide adequate timing margin for PCI clock domains up to 33 MHz. The 164 user I/O pins allow direct connection of a 32-bit address/data bus plus control strobes without external multiplexing, and the 256 macrocells implement wait-state generation, address decoding, and DMA handshake state machines in a single device. MultiVolt I/O lets the 3.3 V core interface with 5 V ISA slots, which is essential when retrofitting industrial PCs. Designers typically compile the bridge logic in Quartus II 13.0sp1 using VHDL or Verilog and program the device over JTAG. The main trade-off is that the MAX 7000A architecture has limited register count compared with modern FPGAs, so complex PCI target controllers may need to be partitioned across two devices.

🌐

Telecommunications Line-Card Control

In telecommunications line cards, the EPM7256AQC208-7 handles control-plane glue logic such as timeslot assignment, framer configuration, and alarm aggregation. Its 256 macrocells and 164 I/O pins can implement multiple independent state machines that monitor T1/E1 or SONET overhead bytes while simultaneously driving status LEDs and backplane control signals. The non-volatile EEPROM configuration ensures the line card reaches a known logic state immediately after power-up, avoiding the configuration latency of SRAM-based FPGAs during hot-swap events. The 7 ns speed grade supports the 125 MHz counter frequency needed for clock-divider chains in telecom timing trees. Because the device is NRND, new line-card designs should migrate to MAX 10 or a small FPGA, but existing deployed cards can continue to be repaired with this part. Thermal design should account for continuous operation in sealed telecom enclosures.

πŸ”§

Test and Measurement Instrumentation

The EPM7256AQC208-7 is well suited to test and measurement instrumentation because its deterministic 7 ns pin-to-pin delay and 227.3 MHz internal toggle rate allow precise event sequencing and trigger generation. Instrument designers use the 256 macrocells to build programmable pulse generators, pattern generators, and digital capture state machines, while the 164 user I/O pins interface directly with front-panel connectors and ADC/DAC control buses. The EEPROM configuration means the instrument boots into a defined state without a configuration PROM, which simplifies field service. MultiVolt I/O supports both 5 V legacy instrumentation buses and 3.3 V modern logic on the same board. A practical limitation is that the MAX 7000A macrocell architecture is coarse-grained, so very deep capture buffers must be implemented in external memory rather than on-chip. The 208-pin PQFP package requires careful thermal relief on dense instrument PCBs.

πŸ’‘

Lighting Control Systems

The EPM7256AQC208-7 is used in lighting control systems, where it implements DMX512 and DALI protocol state machines, dimming PWM generation, and multi-channel relay sequencing. Its 164 user I/O pins can drive dozens of opto-isolated triac or relay channels directly, and the 256 macrocells provide enough registers to hold scene presets and fade tables. The non-volatile EEPROM configuration is a key advantage in lighting controllers because the system must resume its last lighting state immediately after a power interruption, without waiting for an external configuration device. The 3.0-3.6 V core with 5 V-tolerant I/O interfaces cleanly with legacy 5 V dimmer ballasts. Designers should note that the MAX 7000A family is NRND, so new lighting products should consider MAX 10 or a modern flash CPLD; existing installations can continue to be supported with this part.

✈️

Military and Aerospace Legacy Retrofit

The EPM7256AQC208-7 appears in military and aerospace retrofit programs where legacy 5 V logic must be consolidated without a full board redesign. Its 5 V-tolerant MultiVolt I/O and 3.3 V core allow direct replacement of discrete TTL glue logic while reducing board area and power. The 256 macrocells and 164 I/O pins support complex address decoding and bus arbitration for legacy avionics and ground-support equipment. EEPROM configuration provides instant-on operation and immunity to configuration loss during power transients, which is important in ruggedized environments. Because the commercial temperature grade is 0C to +70C, military users must verify that the enclosure maintains this range or select an industrial-temperature MAX 7000A variant. The part is NRND, so long-term support planning should include lifetime buys or a qualified drop-in alternative.

What is the EPM7256AQC208-7?
The EPM7256AQC208-7 is an Altera MAX 7000A-family Complex Programmable Logic Device (CPLD) with 256 macrocells, 5,000 usable gates, and 164 user I/O pins in a 208-pin PQFP package. It is EEPROM-based and in-system programmable, operating from a 3.0 V to 3.6 V core supply with 7 ns pin-to-pin delays.
What are the key specifications of EPM7256AQC208-7 that engineers should know?
The EPM7256AQC208-7 offers 256 macrocells, 5,000 usable gates, 164 maximum user I/O pins, 7 ns pin-to-pin logic delay, 125 MHz maximum counter frequency, and 227.3 MHz internal toggle frequency. It runs on a 3.0-3.6 V core with MultiVolt I/O supporting 5.0 V, 3.3 V, and 2.5 V logic levels, all in a 208-pin PQFP package.
What is the difference between EPM7256AQC208-7 and EPM7256AQC208-7N?
The EPM7256AQC208-7N is the lead-free (RoHS-compliant) version of the EPM7256AQC208-7, with identical electrical specifications: 256 macrocells, 5,000 gates, 7 ns tPD, and the same 208-pin PQFP footprint. The -7N suffix indicates Pb-free construction; both are pin-to-pin compatible and can be used interchangeably on the same PCB.
What is the best drop-in replacement for EPM7256AQC208-7?
The best drop-in replacement is the EPM7256AQC208-7N, which is the lead-free variant with identical 256-macrocell architecture, 7 ns speed grade, and 208-pin PQFP footprint. For higher speed, the EPM7256AQC208-10 offers the same package and macrocell count but a 10 ns delay grade, requiring timing re-verification.
Where to buy EPM7256AQC208-7 online?
EPM7256AQC208-7 is available through DigiKey Marketplace (Rochester Electronics stock), Octopart aggregators, and specialty distributors such as Xecor, Win Source, and IC-Components. As of 2026-09-13, pricing starts at approximately $42.50 for single quantities, with volume discounts at 100+ pieces. Always verify authenticity when sourcing through the open market.
What is the price of EPM7256AQC208-7?
As of 2026-09-13, the EPM7256AQC208-7 is priced at approximately $42.50 for quantity 1, $38.25 at quantity 10, $34.00 at quantity 100, $30.60 at quantity 500, and $27.20 at quantity 1000. Because the MAX 7000A family is mature and sourced largely through Rochester Electronics and the open market, pricing varies significantly by distributor and stock age.
Is EPM7256AQC208-7 in stock?
EPM7256AQC208-7 stock is limited and intermittent because the MAX 7000A family is a mature product line. DigiKey lists it as a Rochester Electronics marketplace item, and Octopart aggregates availability from approximately 3 distributors. As of 2026-09-13, buyers should confirm live stock with each distributor and expect lead times of several weeks for volume orders.
What is the lead time for EPM7256AQC208-7?
Lead time for EPM7256AQC208-7 typically ranges from 2 to 8 weeks depending on distributor stock and order quantity. Since the part is sourced primarily through Rochester Electronics and open-market channels rather than a high-volume production line, buyers should place orders early and consider qualifying a drop-in alternative such as the EPM7256AQC208-7N to mitigate supply risk.
What is the difference between EPM7256AQC208-7 and EPM7256AQC208-10?
The primary difference is speed grade: EPM7256AQC208-7 has a 7 ns pin-to-pin logic delay, while EPM7256AQC208-10 has a 10 ns delay. Both share the same 256 macrocells, 5,000 gates, 208-pin PQFP package, and 3.0-3.6 V supply. The -7 part supports 125 MHz counters versus roughly 100 MHz for the -10 grade.
EPM7256AQC208-7 vs EPM7256AQC208-10 - which is better for high-speed bus interfacing?
For high-speed bus interfacing, the EPM7256AQC208-7 is better because its 7 ns pin-to-pin delay and 125 MHz counter frequency provide more timing margin than the 10 ns EPM7256AQC208-10. If your design has relaxed timing (under 100 MHz), the -10 grade is a lower-cost drop-in with the same 208-pin PQFP footprint.
When should I choose EPM7256AQC208-7 over EPM7256AQC208-10?
Choose the EPM7256AQC208-7 when your design requires pin-to-pin delays below 10 ns, counter frequencies above 100 MHz, or tight setup/hold margins on PCI or high-speed state machines. Choose the EPM7256AQC208-10 when timing is relaxed and cost or availability favors the slower grade, since both share the same 208-pin PQFP footprint.
Is EPM7256AQC208-7 suitable for industrial control applications?
Yes, the EPM7256AQC208-7 is well suited to industrial control applications such as factory automation glue logic, address decoding, and lighting control systems. Its 164 user I/O pins, 5 V-tolerant MultiVolt I/O, and non-volatile EEPROM configuration make it reliable in mixed-voltage industrial environments where instant-on operation and deterministic timing are required.
Where to download EPM7256AQC208-7 datasheet PDF?
The EPM7256AQC208-7 datasheet is available from Intel/Altera's programmable documentation portal and from distributor pages such as DigiKey, Octopart, and DigChip. The MAX 7000A data sheet covers the full family, including the 208-pin PQFP pinout, timing models, and ISP programming specifications. Always download from the manufacturer or an authorized distributor to ensure the current revision.
Where to find EPM7256AQC208-7 pinout?
The EPM7256AQC208-7 pinout is documented in the MAX 7000A family data sheet, which lists all 208 PQFP pins including 164 user I/O, dedicated clock inputs, JTAG (TCK, TMS, TDI, TDO), and power/ground pins. Distributor pages such as Avaq and DigChip also publish pinout diagrams. Verify against the manufacturer data sheet before committing a PCB layout.
What is the best Altera equivalent for EPM7256AQC208-7?
Within the Altera MAX 7000A family, the closest equivalents are the EPM7256AQC208-7N (lead-free, identical speed) and the EPM7256AQC208-10 (same package, slower 10 ns grade). The EPM7256AETC144-7 offers the same 256 macrocells in a smaller 144-pin TQFP package, but it is not pin-compatible with the 208-pin PQFP footprint.
Can EPM7256AQC208-10 replace EPM7256AQC208-7?
Yes, the EPM7256AQC208-10 can replace the EPM7256AQC208-7 on the same 208-pin PQFP footprint, but only if the design tolerates the slower 10 ns pin-to-pin delay versus 7 ns. Both have 256 macrocells and 5,000 gates. Re-run static timing analysis in Quartus II after the swap to confirm all setup and hold requirements are still met.
Hey Google, what can replace EPM7256AQC208-7?
The EPM7256AQC208-7 can be replaced by the EPM7256AQC208-7N (lead-free, identical 7 ns speed) or the EPM7256AQC208-10 (same 208-pin PQFP, 10 ns speed grade). Both are Altera MAX 7000A CPLDs with 256 macrocells and 5,000 gates, so they drop into the same socket with no PCB changes, provided timing is re-verified for the -10 grade.
Is EPM7256AQC208-7 the same as EPM7256AQC208-7N?
No, they are not identical: the EPM7256AQC208-7N is the lead-free (Pb-free) version of the EPM7256AQC208-7. Electrically they are the same part with 256 macrocells, 5,000 gates, 7 ns tPD, and a 208-pin PQFP package. The -7N suffix denotes RoHS-compliant construction, which matters for compliance but not for logic function or pinout.
What software supports EPM7256AQC208-7 design compilation?
The EPM7256AQC208-7 is supported by Altera Quartus II version 13.0sp1 and earlier; later Quartus releases dropped MAX 7000A support. Design entry can use schematic capture, VHDL, or Verilog, and programming is performed via the IEEE 1149.1 JTAG interface. Engineers maintaining legacy designs should archive the Quartus II 13.0sp1 installation because it is no longer actively distributed.
What is the lifecycle status of EPM7256AQC208-7?
The EPM7256AQC208-7 is in NRND (Not Recommended for New Designs) status. The MAX 7000A family is a mature, EEPROM-based CPLD line that Intel/Altera has superseded with MAX II, MAX V, and MAX 10 families. Existing designs can continue to use it, but new designs should migrate to a modern CPLD or small FPGA with an equivalent pin count.

Engineering reference data for EPM7256AQC208-7 β€” comparison, design guidance, and compliance information.

Selection Guide

Choose the EPM7256AQC208-7 when you need a 256-macrocell CPLD with 7 ns pin-to-pin delay, 125 MHz counter operation, and 164 user I/O pins in a 208-pin PQFP, and your design requires the fastest available speed grade for PCI or high-speed state-machine logic. Choose the EPM7256AQC208-7N if your product must be lead-free or RoHS-compliant; it is electrically identical and pin-compatible. Choose the EPM7256AQC208-10 or -10N if your timing budget tolerates 10 ns delays and you want better availability or lower cost. Choose the EPM7256AQC208-5 only if you need the fastest 5 ns grade and can accept its higher price and scarcer supply. Choose the EPM7256AEQC208-7N if you want the low-voltage MAX 7000AE variant with the same footprint. Because the entire MAX 7000A family is NRND, new designs should evaluate MAX 10 or a modern flash CPLD, but existing designs can be sustained with any of these drop-in parts.

Comparison with Alternatives

Parameter This Product EPM7256AQC208-7N EPM7256AQC208-10 EPM7256AQC208-10N EPM7256AQC208-5 EPM7256AQC208-15 EPM7256AEQC208-7N
Package 208-PQFP (28x28) 208-PQFP (28x28) - same 208-PQFP (28x28) - same 208-PQFP (28x28) - same 208-PQFP (28x28) - same 208-PQFP (28x28) - same 208-PQFP (28x28) - same
Brand Altera Altera Altera Altera Altera Altera Altera
Macrocells 256 256 256 256 256 256 256
Usable Gates 5,000 5,000 5,000 5,000 5,000 5,000 5,000
Pin-to-Pin Delay (tPD) 7 ns 7 ns 10 ns 10 ns 5 ns 15 ns 7 ns
Maximum Counter Frequency 125 MHz 125 MHz ~100 MHz ~100 MHz ~147 MHz ~83 MHz 125 MHz
Supply Voltage - Internal 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V
Lead-Free (RoHS) [DATA_NEEDED: RoHS status] Yes (N suffix) [DATA_NEEDED] Yes (N suffix) [DATA_NEEDED] [DATA_NEEDED] Yes (N suffix)
Speed Grade -7 -7 -10 -10 -5 -15 -7
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile)

Key Differentiators

  • Non-volatile EEPROM configuration with instant-on operation (vs EPM7256AQC208-10)
  • Highest speed grade in the 208-pin PQFP MAX 7000A family (vs EPM7256AQC208-15)
  • Lead-free option available with identical electrical performance (vs EPM7256AQC208-7N)
  • High I/O density for bus consolidation (vs EPM7256AETC144-7)

Design Notes

Decouple every VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus at least one 10 uF bulk capacitor per power plane. The MAX 7000A core draws transient current during macrocell switching; inadequate decoupling causes ground bounce that can corrupt EEPROM configuration during ISP. Estimated: at 3.3 V and 100 mA typical core current, a 0.1 uF cap supplies charge for roughly 3 ns of switching before the bulk capacitor responds, so do not omit the bulk capacitor even on lightly loaded boards.

Route the JTAG signals (TCK, TMS, TDI, TDO) as short, matched traces with a continuous ground reference and a 10 kOhm pull-up on TMS and a 10 kOhm pull-down on TCK to prevent accidental ISP entry during normal operation. Keep TCK below 10 MHz during in-system programming to stay within the MAX 7000A ISP timing specification. Place the JTAG header close to the device and avoid routing TCK parallel to high-speed I/O for more than 10 mm.

The 208-pin PQFP package dissipates power primarily through the leadframe and PCB copper. Estimated: at 3.3 V with 150 mA core current, the device dissipates approximately 0.5 W; with a typical PQFP theta_JA of about 40 C/W, junction temperature rises roughly 20 C above ambient. Provide a thermal pad or generous copper area under the device and avoid enclosing it in a sealed, unventilated region. Verify junction temperature against the datasheet maximum for the commercial 0C to +70C grade.

Do not attempt to compile MAX 7000A designs with Quartus II versions later than 13.0sp1 - support was removed and the device will not appear in the device list. Also confirm that the .pof programming file targets the correct speed grade; programming a -7 device with a -10 timing-optimized design is acceptable, but the reverse may violate timing. Always archive the exact Quartus II 13.0sp1 installation and device support files used for production programming.

When driving 5 V peripherals from the 3.3 V core through MultiVolt I/O, verify that the I/O bank VCCIO is set to the peripheral voltage and that series termination (typically 22 to 33 Ohm) is used on long traces exceeding 50 mm. Unterminated 5 V CMOS inputs can cause overshoot above the absolute maximum I/O rating. For bus interfaces above 50 MHz, keep stub lengths under 10 mm and reference all high-speed I/O to a solid ground plane.

Compliance Information

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Lead Free
Unknown
Halogen Free
Unknown
Conflict Minerals
Unknown

Compliance data was not present in the verified web data for EPM7256AQC208-7. The -7N and -10N suffix variants are lead-free (Pb-free) per Altera naming convention, but this was not confirmed in the retrieved data. Verify RoHS/REACH status with the manufacturer or distributor before design release.

Data verified on: 2026-09-13 β€” data verified and curated by XAIPART's component engineering team

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Related Components & Terms

Altera Intel EPM7256AQC208-7 EPM7256AQC208-7N EPM7256AQC208-10 EPM7256AEQC208-7N MAX 7000A CPLD Complex Programmable Logic Device programmable logic device macrocell logic array block EEPROM MultiVolt I/O IEEE 1149.1 JTAG 208-PQFP PQFP family surface mount pin-to-pin logic delay Quartus II RoHS industrial control PCI bus in-system programmable
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