EP1810JI-35 vs EP1810JC-35 Perbandingan

Perbandingan bersamaan detil EP1810JI-35 dari Intel dan EP1810JC-35 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1810JI-35 EP1810JC-35
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family Classic EPLD Classic EPLD (EP1810)
Macrocells 48 —
Logic Array Blocks 8 LABs of 16 macrocells —
Dedicated Inputs 48 —
Pin-to-Pin Propagation Delay (tPD) 35 ns —
Speed Grade -35 —
Paket 28-pin JLCC (J-leaded ceramic, windowed) —
Process Technology CMOS EPROM (UV-erasable) CMOS
Suhu Kerja -40C to +85C (Industrial) —
Tegangan Pemuat 5 V (typical classic EPLD) —
Programmability UV-erase, windowed for lab reprogram —
Tipe Mounting Through-Hole (J-lead) Surface Mount (J-Lead)
Status RoHS [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] Compliant (per Altera listing)
Level MSL [DATA_NEEDED: MSL rating] —
Programming Interface JEDEC fuse file via legacy programmer —
Device Type — UV-Erasable Complex PLD (UV PLD / CPLD)
Number of Macrocells — 48
Propagation Delay (tpd) — 35 ns (max)
Frekuensi Bawah Maximum — [DATA_NEEDED: fmax for this speed grade]
Supply Voltage (Vcc) — 5 V (nominal)
Maximum Supply Voltage — 5.25 V (per distributor listing)
Package Type — CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Number of Terminals — 68
Terminal Form — J-Bend
Rentang Suhu Kerja — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Erasure Method — UV (quartz-windowed ceramic package)
Lead-Free Status — Lead-free (per distributor listing)
Logic Architecture — Programmable AND/OR array with macrocell outputs

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