EP1810JI-35 vs EP1810JC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810JC-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-35 | EP1810JC-35 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD | Classic EPLD (EP1810) |
| Macrocells | 48 | — |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Packhaging | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Volte ng Pagbibigay | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Uri ng Pagpapasok | Through-Hole (J-lead) | Surface Mount (J-Lead) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | Compliant (per Altera listing) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Propagation Delay (tpd) | — | 35 ns (max) |
| Maksimum na Taktiko ng Oras | — | [DATA_NEEDED: fmax for this speed grade] |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Hanay ng Temperature na Operasyon | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |