EP1810LC-45 vs EP1810LC-30 Perbandingan
Perbandingan bersamaan detil EP1810LC-45 dari Rochester Electronics dan EP1810LC-30 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete
Perbandingan Spesifikasi
| Parameter Umum | EP1810LC-45 | EP1810LC-30 |
|---|---|---|
| Merek | Rochester Electronics | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| Paket | 68-pin PLCC (J-lead) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Suhu Kerja | 0 °C to +70 °C (commercial) | [DATA_NEEDED: temperature grade] |
| Tipe Mounting | Surface Mount (PLCC socket compatible) | — |
| Status RoHS | [DATA_NEEDED: RoHS status of Rochester-sourced part] | unknown (legacy ceramic package) |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 48 |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Tegangan Pemuat | — | 5 V (typical) |
| Technology | — | CMOS, low-power (LC) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Jumlah Pin | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |