EP1810LC-45 vs EP1810LC-30 比較
詳細並排比較 EP1810LC-45 由 Rochester Electronics 與 EP1810LC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete
規格比較
| 參數 | EP1810LC-45 | EP1810LC-30 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| 封裝 | 68-pin PLCC (J-lead) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| 工作溫度 | 0 °C to +70 °C (commercial) | [DATA_NEEDED: temperature grade] |
| 安裝類型 | Surface Mount (PLCC socket compatible) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of Rochester-sourced part] | unknown (legacy ceramic package) |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 48 |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| 供應電壓 | — | 5 V (typical) |
| Technology | — | CMOS, low-power (LC) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| 腳位數 | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |