EP1S20F672C7 vs EP1S20F672C6 Perbandingan
Perbandingan bersamaan detil EP1S20F672C7 dari Intel dan EP1S20F672C6 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP1S20F672C7 | EP1S20F672C6 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Series | Stratix | Stratix |
| Family | Altera Stratix FPGA | Stratix (first generation) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | 1,669,248 |
| User I/O Pins | 426 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Paket | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | 672-ball FineLine BGA |
| Logic Family | CMOS, SRAM-based | — |
| Core Supply Voltage | 1.5 V | — |
| Suhu Kerja | 0C to 85C (commercial) | 0°C to +85°C (Commercial) |
| Speed Grade | C7 | C6 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Clock PLLs | Up to 10 | — |
| Manufacturer | — | Altera (now Intel) |
| Process Technology | — | 0.13 µm CMOS |
| Logic Array Blocks (LABs) | — | 1,846 |
| Maximum User I/Os | — | 426 |
| Package Code | — | F672 |
| Tegangan Pemuat | — | Core 1.5 V, I/O programmable |