EP1SGX25DF672I6 vs EP1SGX25DF67216 Perbandingan

Perbandingan bersamaan detil EP1SGX25DF672I6 dari Intel dan EP1SGX25DF67216 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1SGX25DF672I6 EP1SGX25DF67216
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Series Stratix GX —
Family Stratix GX Stratix GX
Logic Elements 25,660 25,660
Total RAM Bits 1,944,576 1,944,576
User I/O Count 455 —
Paket 672-BBGA (FC-FBGA), 33 x 33 mm, 1.0 mm pitch 672-ball FineLine BGA (DF672)
Process Technology 130 nm CMOS —
Core Supply Voltage (VCCINT) 1.5 V —
Suhu Kerja -40C to +85C (industrial, I6 grade) Industrial, -40C to +100C (I-suffix family)
Temperature Grade Industrial (I6) —
Maximum Internal Frequency 5000 MHz (per datasheet header) —
Tipe Mounting Surface Mount Surface Mount (BGA)
Lead Free / RoHS Yes / Compliant —
Jumlah Pin 672 —
DSP Blocks Yes (embedded multipliers) —
On-chip Transceivers Yes (Stratix GX embedded MGTs) —
Clock Management PLLs (on-chip) —
Logic Family / Base Technology CMOS —
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration
Status RoHS — Lead-free / RoHS compliant (per Altera product family documentation)

Spek dan Sumber

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