EP20K200CF484C7N vs EP20K200CF484C8ES Perbandingan
Perbandingan bersamaan detil EP20K200CF484C7N dari Altera dan EP20K200CF484C8ES dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EP20K200CF484C7N - APEX-20K 200K Gates FPGA 484-FBGA | Intel/Altera
EP20K200CF484C7N ObsoleteAltera
EP20K200CF484C8ES - APEX-20KC 200K Gates FPGA | Altera
EP20K200CF484C8ES ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EP20K200CF484C7N | EP20K200CF484C8ES |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Series | APEX-20K | APEX-20KC |
| Logic Elements / Cells | 8,320 | — |
| Total RAM Bits | 106,496 | — |
| Number of Gates (typical) | 200,000 | — |
| Number of I/O | 382 | — |
| Voltage - Supply (VCCINT) | 1.71 V to 1.89 V | — |
| Paket / Case | 484-BBGA (FineLine BGA) | — |
| Supplier Device Package | 484-FBGA (23x23 mm) | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Suhu Kerja | 0C to +85C (commercial grade) | 0C to +85C (commercial) |
| Number of PLLs | 4 | — |
| Embedded Array Blocks (EABs) | Configurable as RAM/ROM/FIFO | — |
| Programmable Logic Blocks | APEX LAB architecture | — |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5V | — |
| Configuration Method | SRAM-based, in-system reconfigurable | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Status Lingkungan Hidup | Obsolete (Altera/Intel APEX-20K family EOL) | — |
| Family | — | APEX 20K |
| Logic Elements | — | 8,320 |
| System Gates | — | 200,000 |
| Embedded Memory (RAM bits) | — | 106,496 |
| Number of Logic Array Blocks (LABs) | — | 104 |
| Number of Embedded System Blocks (ESBs) | — | 13 |
| User I/O Pins (max) | — | 376 |
| PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| Speed Grade | — | C8 (-8 commercial) |
| Paket | — | 484-pin FBGA (FineLine BGA) |
| Process Node | — | 0.18 micron CMOS |
| Configuration Interface | — | JTAG (IEEE 1149.1) / Altera serial |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP |
| Lead Free / RoHS | — | [DATA_NEEDED: lead-free status] |