EP2A25F672C8 vs EP2A25F672C9 Perbandingan

Perbandingan bersamaan detil EP2A25F672C8 dari Altera dan EP2A25F672C9 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP2A25F672C8 EP2A25F672C9
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family APEX II (EP2A25) APEX II
Logic Elements 25,000 (typical gates) —
Maximum System Gates 40,960 —
Macrocells / Embedded Logic 2,432 macros —
User I/O Count 492 —
Paket 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) 672-ball FCBGA (FineLine BGA)
Propagation Delay (tpd) 1.69 ns —
Speed Grade C8 —
Suhu Kerja 0 C to 85 C (commercial) 0°C to 85°C (Commercial)
Process Technology 0.15 microm CMOS, 8-layer copper interconnect 0.15 µm all-layer copper, up to 8 metal layers
I/O Standards Supported LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL —
LVDS Data Rate 1 Gbps —
PLL Count 4 —
Embedded Memory ESB blocks (dual-port RAM, FIFO, CAM, ROM) ESBs for dual-port RAM, ROM, FIFO
I/O Banks 16 —
Tipe Mounting Surface Mount Surface Mount
Status RoHS Non-compliant (legacy product) [DATA_NEEDED]
Logic Elements (LE) — Approximately 25,000
Macro Cells — 2432
User I/O — 492
Package Dimensions — 27 mm x 27 mm
Ball Pitch — 1.0 mm
Logic Family — CMOS
Propagation Delay — 1.69 ns
Tegangan Pemuat — [DATA_NEEDED: core VCC voltage]
I/O Standards — LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V)
Configuration — Passive Serial, Passive Parallel Synchronous, JTAG

Spek dan Sumber

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