EP610IDC-15 vs EP610IDC-10 Perbandingan

Perbandingan bersamaan detil EP610IDC-15 dari Intel dan EP610IDC-10 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Intel
EP610IDC-15 EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EP610IDC-15 EP610IDC-10
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Device Family Altera Classic EPLD Altera Classic EPLD
Macrocells 16 —
Usable Gates 300 —
Propagation Delay (tPD) 15 ns —
Maximum Frequency 66 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal)
Suhu Kerja 0C to +70C (commercial) —
Process Technology CMOS, UV-erasable / OTP —
Paket 24-pin CerDIP (ceramic DIP) —
Tipe Mounting Through-hole Through-hole
I/O Pins 24 (per package; macrocell-programmable) 20
Logic-Block Architecture AND/OR macrocell array with programmable flip-flops —
Program/Erase UV-erasable, OTP-compatible —
Development Tool MAX+PLUS II —
Status RoHS [DATA_NEEDED: RoHS status of CerDIP variant] [DATA_NEEDED: RoHS status of CDIP-10 variant]
Programming Current 11.0 mA typical (per Classic family datasheet) —
Logic Capacity — 300 usable gates
Macrocell Count — 16 macrocells
Pin-to-Pin Logic Delay (tpd) — 10 ns
Maximum Counter Frequency (fCNT) — 100 MHz
I/O Logic Compatibility — 100% TTL emulation
Technology — CMOS, UV-erasable (windowed ceramic)
Package Type — 24-pin Ceramic DIP (CDIP)
Dedicated Inputs — 4
Rentang Suhu Kerja — 0 °C to +70 °C (commercial)
Programmable Interconnect — Yes (on-chip)
In-System Programmability — Yes (via MAX+PLUS II)
Boundary-Scan Test — Yes (per device documentation)

Spek dan Sumber

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