EP610LI-35 vs EP610LC-35 Perbandingan

Perbandingan bersamaan detil EP610LI-35 dari Altera dan EP610LC-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP610LI-35 EP610LC-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Classic EPLD Altera Classic EPLD
Series EP610 —
Number of Macrocells 16 —
Usable Gates 300 300
Number of I/O Pins 16 —
Total Inputs 20 —
Dedicated Inputs 4 —
External Clock Inputs 2 —
Product Terms 160 —
Maximum Propagation Delay 35 ns (tpd) —
Maximum Operating Frequency 28.6 MHz (fmax) —
Pipelined Data Rate Up to 100 MHz —
Tegangan Pemuat 5 V —
Process Technology CMOS —
Architecture PAL-type (AND-OR array) —
Paket 28-pin PLCC (windowed ceramic, 'LI') 28-pin PLCC (J-lead)
Rentang Suhu Kerja [DATA_NEEDED: military/industrial operating temperature range] —
Programming Technology UV-erasable (EPROM) —
Tipe Mounting Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: rohs_status]
Device Series — EP610
Macrocells — 16
Propagation Delay (tpd) — 37 ns
Supply Voltage (Vcc) — 5 V
Technology — CMOS EEPROM (one-time-programmable plastic)
Suhu Kerja — Commercial (0C to +70C) [DATA_NEEDED: exact grade letter]
Speed Grade — -35 (slowest EP610)
Programmable Pins — 24 input / 16 output (shared macrocells)
Lead-Free — [DATA_NEEDED: lead_free]
Level MSL — [DATA_NEEDED: msl_level]
Programming Tool — MAX+PLUS II development system

Spek dan Sumber

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