EP910DC-30 vs EP910DC-35 Perbandingan
Perbandingan bersamaan detil EP910DC-30 dari Intel dan EP910DC-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910DC-30 | EP910DC-35 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | Classic EPLD EP910 |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type sum-of-products AND-OR array |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Tegangan Pemuat | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | JEDEC fuse map via device programmer; UV erase |
| Paket | DIP-40 (through-hole, 600 mil) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Suhu Kerja | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| Tipe Mounting | Through-Hole | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Usable Gates | — | 900 gates |
| Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Frekuensi Bawah Maximum | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Technology | — | CMOS, UV-erasable EPROM cell |
| Status RoHS | — | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |