EP910LI-35T vs EP910LI-40 Perbandingan

Perbandingan bersamaan detil EP910LI-35T dari Intel dan EP910LI-40 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Intel
EP910LI-35T EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel

EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel

EP910LI-35T ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EP910LI-35T EP910LI-40
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Family Classic EPLD (EP910) —
Logic Elements 24 macrocells —
Usable Gates 450 —
Propagation Delay (tPD) 35 ns 40 ns
Maximum Toggle Frequency (fMAX) 28.6 MHz —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, EPROM-based Low-power CMOS (L-suffix)
Paket 44-pin PLCC (JEDEC) PLCC-44 (J-lead, windowed ceramic)
Suhu Kerja -40C to +85C (industrial, 'I' suffix) -40C to +85C (industrial, I-suffix)
Tipe Mounting Surface Mount / Socket Surface Mount (socket-compatible)
Programming Method EPROM (UV-erasable for windowed versions) —
Data Retention [DATA_NEEDED: data retention years] —
Number of I/O Pins [DATA_NEEDED: I/O pin count] —
Status RoHS [DATA_NEEDED: RoHS compliance] Non-compliant (windowed ceramic PLCC, legacy)
Lead-Free [DATA_NEEDED: lead-free status] —
Manufacturer — Altera (now Intel PSG)
Product Family — Classic EPLD - EP910 series
Device Type — Erasable Programmable Logic Device (EPLD)
Macrocells — 24
Dedicated Inputs — 12
I/O Pins — 24 bidirectional
Maximum Logic Inputs — 36
Product Terms — 240
Programmability — UV-erasable, JEDEC-standard algorithm
Lifecycle — Obsolete - replaced by MAX 7000 / MAX II CPLD family

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