EP910PC-20 vs EP910IPC-15 Perbandingan
Perbandingan bersamaan detil EP910PC-20 dari Altera dan EP910IPC-15 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910PC-20 | EP910IPC-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Usable Gates | 900 | — |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Paket | PDIP-24 (PC suffix) | PDIP-40 (Plastic DIP, 40-pin) |
| Jumlah Pin | 24 | 40 |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| Suhu Kerja | 0C to +70C (commercial) | 0C to +70C (commercial, IPC suffix) |
| Programming Method | EPROM programmer, JEDEC fuse map | JEDEC fuse map via Altera EPLD programmer |
| Tipe Mounting | Through-Hole (DIP) | Through-Hole |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type, CMOS |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Propagation Delay (tPD) | — | 15 ns |
| Process Technology | — | CMOS |