EP910PC-20 vs EP910PC-20T Perbandingan

Perbandingan bersamaan detil EP910PC-20 dari Altera dan EP910PC-20T dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP910PC-20 EP910PC-20T
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Unknown
Family Altera Classic EPLD Classic EPLD
Device EP910 —
Usable Gates 900 —
Macrocell Count [DATA_NEEDED: macrocell count] —
Pin-to-Pin Delay (tPD) 20 ns —
Paket PDIP-24 (PC suffix) —
Jumlah Pin 24 —
Supply Voltage (VCC) 5 V —
Technology CMOS EPROM (UV-erasable) —
I/O Compatibility 100% TTL —
Suhu Kerja 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Programming Method EPROM programmer, JEDEC fuse map —
Tipe Mounting Through-Hole (DIP) —
Level MSL [DATA_NEEDED: MSL level] —
Status RoHS [DATA_NEEDED: RoHS status] unknown
Device Type — EPLD
Fabrication Technology — CMOS
Logic Integration — 300 to 900 usable gates
Logic Emulation — 100% TTL emulation
Application Function — High-speed, low-power logic integration
Programmable Device Class — Erasable programmable logic device
Device Family — Altera Classic EPLD Family
Speed Grade — 20 ns
Package Code — PC
Package Pin Count — [DATA_NEEDED: package pin count]
Package Dimensions — [DATA_NEEDED: package dimensions]
Tegangan Pemuat — [DATA_NEEDED: operating supply voltage]
I/O Count — [DATA_NEEDED: I/O count]
Internal Logic Capacity — 300 to 900 usable gates
Supported Logic Integration — Multiple PAL- and GAL-type devices
Programming Interface — [DATA_NEEDED: programming interface]
Programming Voltage — [DATA_NEEDED: programming voltage]
Mounting Technology — [DATA_NEEDED: mounting technology]
REACH Status — unknown
AEC-Q100 Qualification — not_applicable
Lead-Free Status — unknown
Halogen-Free Status — unknown

Spek dan Sumber

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