EP910PI-25T vs EP910PI-20 Perbandingan

Perbandingan bersamaan detil EP910PI-25T dari Altera dan EP910PI-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP910PI-25T EP910PI-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Altera Classic EPLD Family —
Macrocells 24 24
Equivalent Gates 900 (SSI/MSI equivalent) —
Maximum Inputs 36 —
Maximum Outputs 24 —
Propagation Delay (tpd) 25 ns —
Supply Voltage (VCC) 5 V 5 V (+/- 5%)
Technology CMOS, UV-erasable EPROM CMOS EPROM (UV-erasable windowed variants available)
Paket 40-pin PDIP (600-mil) PDIP-40 (PI suffix)
Suhu Kerja [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Programming UV-erasable —
Tipe Mounting Through-Hole (DIP) Through-Hole
Status RoHS [DATA_NEEDED: RoHS compliance] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Static Power <100 mW (typical CMOS) —
Device Family — Altera Classic EPLD Family
Propagation Delay (tPD) — 20 ns
Configuration Method — Non-volatile EPROM (no boot PROM required)
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

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