EP910PI-25T vs EP910PI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-25T sa pamamagitan ng Altera at EP910PI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-25T | EP910PI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Equivalent Gates | 900 (SSI/MSI equivalent) | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Supply Voltage (VCC) | 5 V | 5 V (+/- 5%) |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM (UV-erasable windowed variants available) |
| Packhaging | 40-pin PDIP (600-mil) | PDIP-40 (PI suffix) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Programming | UV-erasable | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Static Power | <100 mW (typical CMOS) | — |
| Device Family | — | Altera Classic EPLD Family |
| Propagation Delay (tPD) | — | 20 ns |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |