EPC164C88N vs EPC16JC88 Perbandingan

Perbandingan bersamaan detil EPC164C88N dari Intel dan EPC16JC88 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC164C88N EPC16JC88
Merek Intel Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup NRND NRND
Fungsi In-system programmable configuration PROM for SRAM-based FPGAs —
Memory Density 16 Mbit —
Configuration Interface Altera passive serial / fast passive parallel Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE)
Programming Interface IEEE 1149.1 JTAG (in-system programmable) JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO
Operating Voltage (VCCINT) 3.3 V typical —
Supported FPGA Voltages 1.8 V, 2.5 V, 3.3 V, 5.0 V —
Paket 88-pin UBGA (Ultra FineLine BGA) 11x8 mm 88-ball UBGA (11 x 8 mm), JEDEC designation C88
Tipe Mounting Surface Mount (BGA) —
Rentang Suhu Kerja [DATA_NEEDED: industrial or commercial grade] —
Level MSL [DATA_NEEDED: MSL classification] —
Status RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance declaration]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free finish]
REACH Status [DATA_NEEDED: REACH compliance] —
Compatible FPGA Families Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix GX, Stratix II GX, HardCopy II —
Configuration Mode Passive Serial (PS), Fast Passive Parallel (FPP) —
Reprogrammability Yes (in-system via JTAG) —
Manufacturer — Altera (now Intel FPGA)
Family — Enhanced Configuration Device (EPC4 / EPC8 / EPC16)
Device Function — In-system programmable configuration PROM for SRAM-based FPGAs
Density — 16 Mbit
Programmability — In-system programmable via IEEE 1149.1 JTAG
Operating Temperature Grade — Industrial (J suffix)
Tegangan Pemuat — [DATA_NEEDED: VCC operating range]
Supported FPGA Families — Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface)
Configuration Clock — Driven by target FPGA during configuration
Multi-Device Configuration — Supports daisy-chain configuration of multiple FPGAs
Tingkat Sensitivitas Kekeringan (MSL) — [DATA_NEEDED: MSL rating per JEDEC J-STD-020]
Bebas Halogen — [DATA_NEEDED: halogen-free status]

Spek dan Sumber

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