EPC164C88N vs EPC16JC88 비교
다음의 상세 나란히 비교: EPC164C88N 제조: Intel 및 EPC16JC88 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPC164C88N | EPC16JC88 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | Memory ICs | Memory ICs |
| 수명 주기 상태 | NRND | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $7.20 | $17.95 |
| 기능 | In-system programmable configuration PROM for SRAM-based FPGAs | — |
| Memory Density | 16 Mbit | — |
| Configuration Interface | Altera passive serial / fast passive parallel | Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO |
| Operating Voltage (VCCINT) | 3.3 V typical | — |
| Supported FPGA Voltages | 1.8 V, 2.5 V, 3.3 V, 5.0 V | — |
| 패키지 | 88-pin UBGA (Ultra FineLine BGA) 11x8 mm | 88-ball UBGA (11 x 8 mm), JEDEC designation C88 |
| 실장 유형 | Surface Mount (BGA) | — |
| 동작 온도 범위 | [DATA_NEEDED: industrial or commercial grade] | — |
| MSL 레벨 | [DATA_NEEDED: MSL classification] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance declaration] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free finish] |
| REACH Status | [DATA_NEEDED: REACH compliance] | — |
| Compatible FPGA Families | Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix GX, Stratix II GX, HardCopy II | — |
| Configuration Mode | Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| Reprogrammability | Yes (in-system via JTAG) | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Family | — | Enhanced Configuration Device (EPC4 / EPC8 / EPC16) |
| Device Function | — | In-system programmable configuration PROM for SRAM-based FPGAs |
| Density | — | 16 Mbit |
| Programmability | — | In-system programmable via IEEE 1149.1 JTAG |
| Operating Temperature Grade | — | Industrial (J suffix) |
| 공급 전압 | — | [DATA_NEEDED: VCC operating range] |
| Supported FPGA Families | — | Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface) |
| Configuration Clock | — | Driven by target FPGA during configuration |
| Multi-Device Configuration | — | Supports daisy-chain configuration of multiple FPGAs |
| 습도 민감도 레벨 (MSL) | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| 할로겐 프리 | — | [DATA_NEEDED: halogen-free status] |