EPC16UC88 vs EPC16U88 Perbandingan
Perbandingan bersamaan detil EPC16UC88 dari Altera dan EPC16U88 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC16UC88 | EPC16U88 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | FPGA & CPLD |
| Status Lingkungan Hidup | Unknown | Obsolete |
| Device Type | In-system programmable configuration PROM for FPGAs | — |
| Configuration Memory Capacity | 16 Mb | — |
| Tegangan Pemuat | 3.3 V core and I/O | — |
| Paket | 88-UBGA (11x8) | 88-ball UBGA (UltraBGA), 11x8 mm |
| Package Family | UBGA | — |
| In-System Programmability | IEEE Std. 1532 compatible | — |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | — |
| JTAG Boundary Scan | Supported | — |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | — |
| Configuration Architecture | Configuration controller and flash memory | — |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | — |
| Data Output | Configuration data output controlled by OE and nCS | — |
| Output Control | OE and nCS control tri-state buffer and address counter | — |
| Tipe Mounting | Surface mount | — |
| Package Dimensions | 11 mm x 8 mm | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature] | -40C to +85C (industrial) |
| Output Current | [DATA_NEEDED: output current] | — |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Memory Density | — | 16 Mb |
| Device Family | — | EPC16 (Enhanced Configuration Device) |
| Fungsi | — | Configuration PROM for SRAM-based LUT FPGAs |
| Package Suffix Code | — | U88 (UBGA-88) |
| Supply Voltage (VCC) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5 V tolerant I/O |
| Configuration Modes Supported | — | FPP, PS, AS (with target FPGA) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Multi-Device Cascading | — | Yes (page-mode support) |
| Compatible FPGA Families | — | Altera Stratix, Cyclone, Arria series |
| Configuration Interface Width | — | Up to 8-bit parallel (FPP) |
| Level MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |