EPC1LC20C vs EPC2LC20 Perbandingan
Perbandingan bersamaan detil EPC1LC20C dari Altera dan EPC2LC20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC1LC20C | EPC2LC20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | Memory ICs |
| Status Lingkungan Hidup | NRND | NRND |
| Tipe Memori | Serial Configuration Flash | Non-volatile configuration PROM |
| Ukuran Memori | 1 Mbit (1,048,576 bits) | 1.6 Mbit |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Antarmuka | Serial (DATA/DCLK) + JTAG (IEEE 1149.1) | — |
| Tegangan Pemuat | 3.3 V or 5.0 V | — |
| Programmability | In-system via JTAG | — |
| Cascading Support | Yes (nCS, CS pins) | — |
| Paket | 20-pin LCC (Leadless Chip Carrier) | 20-pin PLCC (J-lead, 9x9 mm) |
| Tipe Mounting | Surface Mount (ceramic) | Surface Mount |
| Suhu Kerja | -40C to +85C (industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K | — |
| JTAG Pins | TCK, TMS, TDI, TDO | — |
| Configuration Mode | Slave-serial (FPGA-master) | — |
| Level MSL | MSL3 (ceramic, floor life 168 hours) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (original Altera Pb-containing part) |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |